SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Figure 12-1790 and Table 12-3438 show an error detect and recovery sequence.
Step | Description |
---|---|
1 | Read eMMC host controller MMCSD0_ERROR_INTR_STS register and determine error is related to CQE. |
2 | Write '1' to MMCSD0_CQ_CONTROL[0] HALT_BIT bit to halt CQE. |
3 | Wait for MMCSD0_CQ_CONTROL[0] HALT_BIT bit to read '1'. In some error cases, this may not happen, so software should proceed to the next step after a sufficient time-out. |
4 | Read MMCSD0_CQ_CMD_RESP_INDEX and MMCSD0_CQ_CMD_RESP_ARG registers to determine last response's index and argument. |
5 | Read MMCSD0_CQ_TASK_ERR_INFO register to determine the transmitted command's index and the index of the task to which it is related. |
6 | Perform error-specific recovery procedure. |
7 | Write '0' to MMCSD0_CQ_CONTROL register to resume operation. |