Note: For validated set of parameters
that can be programmed to PLLs, please refer to the device-specific
Datasheet.
Initially, the device powers up in PLL bypass
mode. The bypass mux is a glitch free mux and is located outside the PLL module.
BYPASS_EN bit controls the bypass mux section. During Power-up, the bypass mux
defaults to select FREF clock (PLL clock bypass mode).
During boot, DMSC0 ROM programs the MCU_PLL0 to a
valid frequency based on the crystal frequency and BOOTMODE pin settings. DMSC0 then
waits for PLL to be locked by checking the PLL LOCK status bit. DMSC0 ROM programs
BYPASS_EN bit to ‘0’ to disable the bypass mode to propagate MCU_PLL0 clock to
MCU_PLLCTRL0. At this point DMSC0 brings MCU_M4FSS out of reset to complete the
reset of the boot process. M4FSS software configures the remaining PLLs and bring
them out of bypass mode.
The following shows the PLL
initialization sequence.
- Wait until supplies are stable
and PORz is de-asserted. By this time the reference clock source must be up and
running.
- Default controls settings:
- By default PLL_EN signal
is Low provided by <PLL_name>_CTRL register default state. This
signal behaves like a reset control to the PLL.
- By default INTL_BYP_EN
signal is low provided by <PLL_name>_CTRL register default
state.
- By default BYPASS_EN
signal is high provided by PLL MMR CTRL default state. PLL clock will be
bypassed externally by a glitch free mux. The output of the mux will be
the reference clock FREF.
- LOCK output of PLL will
be Low.
- Program the PLL to a valid
setting that runs the VCO within the specified range. The following
bits/bitfields must be programmed appropriately by software: DSM_EN, DAC_EN,
CLK_POSTDIV_EN, CLK_4PH_EN, REF_DIV[5-0], FB_DIV[11-0], FB_DIV_FRAC[23-0],
POST_DIV1[2-0], POST_DIV2[2-0].
- Wait for 1 µs to allow the PLL
internal reset to complete (PLL powerdown switch pulls the loop filter voltage
from rail-to-rail, which ensures the PLL will be completely powered down from
any state).
- Assert PLL_EN to a High (by
writing a '1' into PLL_EN bit in <PLL_name>_CTRL register).
- Wait for PLL Lock output to go
high. Software can read the LOCK bit in <PLL_name>_STATS register to check
if PLL has locked.
- De-assert BYPASS_EN signal to a
Low by writing 0 into BYPASS_EN bit in <PLL_name>_CTRL register.
- Glitch free mux safely switches
to the PLL clock output.
Changing PLL setting: During normal
operation, before changing PLL settings, the PLL clock must be bypassed by setting
BYPASS_EN control to a high. Then follow steps 2 to 8 from the above sequence.