SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-4841 lists the memory-mapped registers for the ESM. All register offset addresses not listed in Table 12-4841 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
ESM0_CFG | 0042 0000h |
MCU_ESM0_CFG | 0410 0000h |
Offset | Acronym | Register Name | ESM0_CFG Physical Address | MCU_ESM0_CFG Physical Address |
---|---|---|---|---|
0h | ESM_PID | Revision Register | 0042 0000h | 0410 0000h |
4h | ESM_INFO | Info Register | 0042 0004h | 0410 0004h |
8h | ESM_EN | Global Enable Register | 0042 0008h | 0410 0008h |
Ch | ESM_SFT_RST | Global Soft Reset Register | 0042 000Ch | 0410 000Ch |
10h | ESM_ERR_RAW | Config Error Raw Status/Set Register | 0042 0010h | 0410 0010h |
14h | ESM_ERR_STS | Config Error Interrupt Enable Status/Clear Register | 0042 0014h | 0410 0014h |
18h | ESM_ERR_EN_SET | Config Error Interrupt Enable Set Register | 0042 0018h | 0410 0018h |
1Ch | ESM_ERR_EN_CLR | Config Error Interrupt Enabled Clear Register | 0042 001Ch | 0410 001Ch |
20h | ESM_LOW_PRI | Low Priority Prioritized Register | 0042 0020h | 0410 0020h |
24h | ESM_HI_PRI | High Priority Prioritized Register | 0042 0024h | 0410 0024h |
28h | ESM_LOW | Low Priority Interrupt Status Register | 0042 0028h | 0410 0028h |
2Ch | ESM_HI | High Priority Interrupt Status Register | 0042 002Ch | 0410 002Ch |
30h | ESM_EOI | ESM_EOI Interrupt Register | 0042 0030h | 0410 0030h |
40h | ESM_PIN_CTRL | Error Pin Control Register | 0042 0040h | 0410 0040h |
44h | ESM_PIN_STS | Error Pin Status Register | 0042 0044h | 0410 0044h |
48h | ESM_PIN_CNTR | Error Pin Counter Value Register | 0042 0048h | 0410 0048h |
4Ch | ESM_PIN_CNTR_PRE | Error Pin Counter Value Pre-Load Register | 0042 004Ch | 0410 004Ch |
50h | ESM_PWMH_PIN_CNTR | Error Pin PWM High Counter Value Register | 0042 0050h | 0410 0050h |
54h | ESM_PWMH_PIN_CNTR_PRE | Error Pin PWM High Counter Pre-Load Register | 0042 0054h | 0410 0054h |
58h | ESM_PWML_PIN_CNTR | Error Pin PWM Low Counter Value Register | 0042 0058h | 0410 0058h |
5Ch | ESM_PWML_PIN_CNTR_PRE | Error Pin PWM Low Counter Pre-Load Register | 0042 005Ch | 0410 005Ch |
400h + formula | ESM_RAW_j | Config Error Raw Status/Set Register | 0042 0400h + formula | 0410 0400h + formula |
404h + formula | ESM_STS_j | Level Error Interrupt Enable Status/Clear Register | 0042 0404h + formula | 0410 0404h + formula |
408h + formula | ESM_INTR_EN_SET_j | Level Error Interrupt Enable Set Register | 0042 0408h + formula | 0410 0408h + formula |
40Ch + formula | ESM_INTR_EN_CLR_j | Level Error Interrupt Enabled Clear Register | 0042 040Ch + formula | 0410 040Ch + formula |
410h + formula | ESM_INT_PRIO_j | Level Error Interrupt Enabled Clear Register | 0042 0410h + formula | 0410 0410h + formula |
414h + formula | ESM_PIN_EN_SET_j | Level Error Interrupt Enabled Clear Register | 0042 0414h + formula | 0410 0414h + formula |
418h + formula | ESM_PIN_EN_CLR_j | Level Error Interrupt Enabled Clear Register | 0042 0418h + formula | 0410 0418h + formula |
ESM_PID is shown in Figure 12-2538 and described in Table 12-4843.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0000h |
MCU_ESM0_CFG | 0410 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNC | |||||||||||||
R-1h | R-2h | R-FE0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-9h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | ESM_PID register scheme Always reads as 1h. Writes have no affect. |
29-28 | BU | R | 2h | Business Unit: 2h = Processors |
27-16 | FUNC | R | FE0h | Module ID. Always read as the assigned functional ID. Writes have no affect. |
15-11 | RTL | R | 9h | RTL revision. Will vary depending on release. |
10-8 | MAJOR | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom. Special version. |
5-0 | MINOR | R | 0h | Minor revision |
ESM_INFO is shown in Figure 12-2539 and described in Table 12-4845.
Return to Summary Table.
The Info Register gives the configuration information of this ESM.
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0004h |
MCU_ESM0_CFG | 0410 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
LAST_RESET | RESERVED | ||||||
R-0h | R-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PULSE_GROUPS | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GROUPS | |||||||
R-X | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | LAST_RESET | R | 0h | This bit indicates whether the last reset was a Warm or Power-On Rest |
30-16 | RESERVED | R | X | Always read as 0h. Writes have no affect. |
15-8 | PULSE_GROUPS | R | X (see description) | Indicates the number of event groups that are
pulse (as opposed to level) driven. |
7-0 | GROUPS | R | X (see description) | Indicates the total number of groups that exist in
the ESM. |
ESM_EN is shown in Figure 12-2540 and described in Table 12-4847.
Return to Summary Table.
The Global Enable Register has the controller interrupt mask
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0008h |
MCU_ESM0_CFG | 0410 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | KEY | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | Always read as 0h. Writes have no affect. |
3-0 | KEY | R/W | 0h | This field is the global mask for all interrupts. It is reset by the warm reset. The purpose is to leave all of the raw status and per-interrupt enable bits alone so that, after a warm reset, software may observe the state of the ESM before the warm reset and try to debug what may have caused the reset. |
ESM_SFT_RST is shown in Figure 12-2541 and described in Table 12-4849.
Return to Summary Table.
The Global Soft Reset Register controls the global clear for raw status and enables
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 000Ch |
MCU_ESM0_CFG | 0410 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | KEY | ||||||||||||||||||||||||||||||
W-X | W-0h | ||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | X | Always read as 0h. Writes have no affect. |
3-0 | KEY | W | 0h | Global Soft Reset field. Writing to this field can cause all of the raw status and all enables to be cleared. This can be used to reset the ESM state after debugging because of a warm reset. |
ESM_ERR_RAW is shown in Figure 12-2542 and described in Table 12-4851.
Return to Summary Table.
Raw Status/Set Register for Configuration Errors
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0010h |
MCU_ESM0_CFG | 0410 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STS | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | Always read as 0h. Writes have no affect. |
7-0 | STS | R/W1S | 0h | This is the raw status for errors in the
configuration for Group N. This field is only reset by a
Power-On-Reset (not warm reset). A global soft reset will set
this field to 0h. |
ESM_ERR_STS is shown in Figure 12-2543 and described in Table 12-4853.
Return to Summary Table.
Config Error Enable and Clear Register
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0014h |
MCU_ESM0_CFG | 0410 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSK | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | Always read as 0h. Writes have no affect. |
7-0 | MSK | R/W1C | 0h | This is the masked status for errors in the
configuration for Group N. This field is only reset by a
Power-On-Reset (not warm reset). A global soft reset will set
this field to 0. |
ESM_ERR_EN_SET is shown in Figure 12-2544 and described in Table 12-4855.
Return to Summary Table.
Config Error Enable Set Register
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0018h |
MCU_ESM0_CFG | 0410 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSK | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | Always read as 0h. Writes have no affect. |
7-0 | MSK | R/W1S | 0h | This is the mask enable for errors in the
configuration for Group N. If the corresponding bit and the
ESM_EN are set, then the interrupt is unmasked. This field is
only reset by a Power-On-Reset (not warm reset). A global soft
reset will set this field to 0. |
ESM_ERR_EN_CLR is shown in Figure 12-2545 and described in Table 12-4857.
Return to Summary Table.
Config Error Interrupt Enabled Clear register
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 001Ch |
MCU_ESM0_CFG | 0410 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSK | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | Always read as 0h. Writes have no affect. |
7-0 | MSK | R/W1C | 0h | This is the mask clear for errors in the
configuration for Group N. If the corresponding bit and the
ESM_EN are set, then the interrupt is unmasked. This field is
only reset by a Power-On-Reset (not warm reset). A global soft
reset will set this field to 0. |
ESM_LOW_PRI is shown in Figure 12-2546 and described in Table 12-4859.
Return to Summary Table.
Shows which is the highest priority outstanding low priority interrupt
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0020h |
MCU_ESM0_CFG | 0410 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLS | LVL | ||||||||||||||||||||||||||||||
R-FFFFh | R-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | PLS | R | FFFFh | Indicates what the highest priority low priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x2. A value of all ones (0xFFFF) indicates that there are no low priority interrupts pending. |
15-0 | LVL | R | FFFFh | Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for High Priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x2. A value of all ones (0xFFFF) indicates that there are no low priority interrupts pending. |
ESM_HI_PRI is shown in Figure 12-2547 and described in Table 12-4861.
Return to Summary Table.
Shows which is the highest priority outstanding high priority interrupt
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0024h |
MCU_ESM0_CFG | 0410 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLS | LVL | ||||||||||||||||||||||||||||||
R-FFFFh | R-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | PLS | R | FFFFh | Indicates what the highest priority high priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x0. A value of all ones (0xFFFF) indicates that there are no high priority interrupts pending. |
15-0 | LVL | R | FFFFh | Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x0. A value of all ones (0xFFFF) indicates that there are no high priority interrupts pending. |
ESM_LOW is shown in Figure 12-2548 and described in Table 12-4863.
Return to Summary Table.
Shows which groups have outstanding low priority interrupts
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0028h |
MCU_ESM0_CFG | 0410 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STS | R | 0h | Indicates which Event Groups have one or more low priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0, bit 1 is for Event Group 1, etc… (bit N is for Event Group N). |
ESM_HI is shown in Figure 12-2549 and described in Table 12-4865.
Return to Summary Table.
Shows which groups have outstanding high priority interrupts
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 002Ch |
MCU_ESM0_CFG | 0410 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STS | R | 0h | Indicates which Event Groups have one or more high priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0, bit 1 is for Event Group 1, etc… (bit N is for Event Group N). |
ESM_EOI is shown in Figure 12-2550 and described in Table 12-4867.
Return to Summary Table.
End of Interrupt Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0030h |
MCU_ESM0_CFG | 0410 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | KEY | ||||||||||||||||||||||||||||||
W-X | W-0h | ||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | W | X | Always read as 0h. Writes have no affect. |
10-0 | KEY | W | 0h | This is the interrupt being serviced. Writing the corresponding vector to this field will cause a re-evaluation of interrupts. If, when the vector is written, there are still pending interrupts, a new pulse will be generated. Reads always return 0. |
ESM_PIN_CTRL is shown in Figure 12-2551 and described in Table 12-4869.
Return to Summary Table.
This register controls the SAFETY_ERRORn pin output
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0040h |
MCU_ESM0_CFG | 0410 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWM_EN | KEY | |||||||||||||||||||||||||||||
R-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Always read as 0h. Writes have no affect. |
7-4 | PWM_EN | R/W | 0h | PWM mode enable. This field should only be
modified when the ESM is disabled, from the ESM_EN register.
This field is only reset by a Power-On-Reset (not warm reset). A
global soft reset will set this field to 0. |
3-0 | KEY | R/W | 0h | Pin control key. This field controls behavior of the error pin. Note, during reset the field is 0h, but the error pin is asserted (active low). Immediately after reset, the error pin de-asserts. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. A global soft reset will also CLEAR all pending faults. |
ESM_PIN_STS is shown in Figure 12-2552 and described in Table 12-4871.
Return to Summary Table.
This register reflects the status of the error_pin_n output
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0044h |
MCU_ESM0_CFG | 0410 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL | ||||||||||||||
R-X | R-X | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | Always read as 0h. Writes have no affect. |
0 | VAL | R | X (see description) | This field indicates the status of the error pin as looped back from the I/O. This field reflects the state of the ERR_I pin. Since the ERR_O pin is only affected by Power-On-Reset, then the value of this field may be 1h after the release of Warm Reset. |
ESM_PIN_CNTR is shown in Figure 12-2553 and described in Table 12-4873.
Return to Summary Table.
This register shows the current value of the error pin counter
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0048h |
MCU_ESM0_CFG | 0410 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | X | Always read as 0h. Writes have no affect. |
23-0 | COUNT | R | 0h | This field indicates the current value of the time
interval counter. See ESM_PIN_CNTR_PRE register for a
description. This register is reloaded to the counter_preload
value on entry to the ESM_ERROR state from ESM_IDLE and counts
down by one per clock cycle. Once the counter has reached 0, the
minimum time interval has expired. |
ESM_PIN_CNTR_PRE is shown in Figure 12-2554 and described in Table 12-4875.
Return to Summary Table.
This register contains the value that is loaded in to the Error Counter
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 004Ch |
MCU_ESM0_CFG | 0410 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Always read as 0h. Writes have no affect. |
23-0 | COUNT | R/W | 0h | This is the value that will be pre-loaded in to
the ESM_PIN_CNTR[23-0] COUNT bit field whenever the ESM enters
the ESM_ERROR state from ESM_IDLE. The default value is
determined based on the ESM clock frequency, so that there is a
minimum low time of 100µs. |
ESM_PWMH_PIN_CNTR is shown in Figure 12-2555 and described in Table 12-4877.
Return to Summary Table.
This register contains the current value of the PWM High Time Interval Counter.
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0050h |
MCU_ESM0_CFG | 0410 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Always read as 0h. Writes have no affect. |
23-0 | COUNT | R | 0h | This field indicates the current value of the PWM
High Time Interval Counter. If ESM_PIN_CTRL[7-4] PWM_EN is set
to PWM mode, then this register is enabled. This register is
reloaded to the PWM high counter_preload value when the error
output pin toggles high. It will decrement by 1 each cycle when
the error output pin is high. Once the counter has reached 0,
the error output pin will toggle low. |
ESM_PWMH_PIN_CNTR_PRE is shown in Figure 12-2556 and described in Table 12-4879.
Return to Summary Table.
This register contains the value that is loaded in to the Error Pin PWM High Counter Value Register.
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0054h |
MCU_ESM0_CFG | 0410 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Always read as 0h. Writes have no affect. |
23-0 | COUNT | R/W | 0h | This is the value that will be loaded in to the
ESM_PWMH_PIN_CNTR[23-0] COUNT field whenever the error output
pin toggles high. The default value is determined based on the
external PMIC settings. |
ESM_PWML_PIN_CNTR is shown in Figure 12-2557 and described in Table 12-4881.
Return to Summary Table.
This register contains the current value of the PWM Low Time Interval Counter.
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0058h |
MCU_ESM0_CFG | 0410 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Always read as 0h. Writes have no affect. |
23-0 | COUNT | R | 0h | This field indicates the current value of the PWM
Low Time Interval Counter. If ESM_PIN_CTRL[7-4] PWM_EN is set to
PWM mode, then this register is enabled. This register is
reloaded to the PWM low counter_preload value when the error
output pin toggles low. It will decrement by 1 each cycle when
the error output pin is low. Once the counter has reached 0, the
error output pin will toggle high. |
ESM_PWML_PIN_CNTR_PRE is shown in Figure 12-2558 and described in Table 12-4883.
Return to Summary Table.
This register contains the value that is loaded in to the Error Pin PWM Low Counter Value Register.
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 005Ch |
MCU_ESM0_CFG | 0410 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Always read as 0h. Writes have no affect. |
23-0 | COUNT | R/W | 0h | This is the value that will be loaded in to the
ESM_PWML_PIN_CNTR[23-0] COUNT field whenever the error output
pin toggles low. The default value is determined based on the
external PMIC settings. |
ESM_RAW_j is shown in Figure 12-2559 and described in Table 12-4885.
Return to Summary Table.
Raw Status/Set Register for Group A Errors
Offset = 400h + (j * 20h); where
j = 0h to 2h for MCU_ESM0_CFG
j = 0h to 5h for ESM0_CFG
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0400h + formula |
MCU_ESM0_CFG | 0410 0400h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS | |||||||||||||||||||||||||||||||
R/W1S-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STS | R/W1S | 0h | This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc…) |
ESM_STS_j is shown in Figure 12-2560 and described in Table 12-4887.
Return to Summary Table.
Error Enable and Clear Register
Offset = 404h + (j * 20h); where
j = 0h to 2h for MCU_ESM0_CFG
j = 0h to 5h for ESM0_CFG
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0404h + formula |
MCU_ESM0_CFG | 0410 0404h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1C | 0h | This is the masked status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. |
ESM_INTR_EN_SET_j is shown in Figure 12-2561 and described in Table 12-4889.
Return to Summary Table.
Level Error Enable Set Register
Offset = 408h + (j * 20h); where
j = 0h to 2h for MCU_ESM0_CFG
j = 0h to 5h for ESM0_CFG
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0408h + formula |
MCU_ESM0_CFG | 0410 0408h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1S-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1S | 0h | This field is used to enable the mask of events in
group N. Each bit corresponds to event Q where Q = N*32+Bit
(Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc…) If the
corresponding bit and the global enable ESM_EN are set, then the
interrupt is unmasked. This field is only reset by a
Power-On-Reset (not warm reset). A global soft reset will set
this field to 0. |
ESM_INTR_EN_CLR_j is shown in Figure 12-2562 and described in Table 12-4891.
Return to Summary Table.
Level Error Interrupt Enabled Clear register
Offset = 40Ch + (j * 20h); where
j = 0h to 2h for MCU_ESM0_CFG
j = 0h to 5h for ESM0_CFG
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 040Ch + formula |
MCU_ESM0_CFG | 0410 040Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1C | 0h | This field is used to disable the mask of events
in group N. Each bit corresponds to event Q where Q = N*32+Bit
(Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc…) If the
corresponding bit and the global enable ESM_EN are set, then the
interrupt is unmasked. This field is only reset by a
Power-On-Reset (not warm reset). A global soft reset will set
this field to 0. |
ESM_INT_PRIO_j is shown in Figure 12-2563 and described in Table 12-4893.
Return to Summary Table.
Level Error Interrupt Enabled Clear register
Offset = 410h + (j * 20h); where
j = 0h to 2h for MCU_ESM0_CFG
j = 0h to 5h for ESM0_CFG
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0410h + formula |
MCU_ESM0_CFG | 0410 0410h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W | 0h | This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. |
ESM_PIN_EN_SET_j is shown in Figure 12-2564 and described in Table 12-4895.
Return to Summary Table.
Level Error Interrupt Enabled Clear register
Offset = 414h + (j * 20h); where
j = 0h to 2h for MCU_ESM0_CFG
j = 0h to 5h for ESM0_CFG
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0414h + formula |
MCU_ESM0_CFG | 0410 0414h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1S-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1S | 0h | This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. |
ESM_PIN_EN_CLR_j is shown in Figure 12-2565 and described in Table 12-4897.
Return to Summary Table.
Level Error Interrupt Enabled Clear register
Offset = 418h + (j * 20h); where
j = 0h to 2h for MCU_ESM0_CFG
j = 0h to 5h for ESM0_CFG
Instance | Physical Address |
---|---|
ESM0_CFG | 0042 0418h + formula |
MCU_ESM0_CFG | 0410 0418h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1C | 0h | This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. |