SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see Section 12.5.2.1.2, RTI Not Supported Features.
Table 12-4625 lists the memory-mapped registers for the RTI. All register offset addresses not listed in Table 12-4625 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
RTI0_CFG | 0E00 0000h |
RTI1_CFG | 0E01 0000h |
RTI8_CFG | 0E08 0000h |
RTI9_CFG | 0E09 0000h |
RTI10_CFG | 0E0A 0000h |
RTI11_CFG | 0E0B 0000h |
MCU_RTI0_CFG | 0488 0000h |
Offset | Acronym | Register Name | RTI0_CFG Physical Address | RTI1_CFG Physical Address |
---|---|---|---|---|
0h | RTI_GCTRL | RTI Global Control Register | 0E00 0000h | 0E01 0000h |
4h | RTI_TBCTRL | RTI Timebase Control Register | 0E00 0004h | 0E01 0004h |
8h | RTI_CAPCTRL | RTI Capture Control Register | 0E00 0008h | 0E01 0008h |
Ch | RTI_COMPCTRL | RTI Compare Control Register | 0E00 000Ch | 0E01 000Ch |
10h | RTI_FRC0 | RTI Free Running Counter 0 Register | 0E00 0010h | 0E01 0010h |
14h | RTI_UC0 | RTI Up Counter 0 Register | 0E00 0014h | 0E01 0014h |
18h | RTI_CPUC0 | RTI Compare Up Counter 0 Register | 0E00 0018h | 0E01 0018h |
20h | RTI_CAFRC0 | RTI Capture Free Running Counter 0 Register | 0E00 0020h | 0E01 0020h |
24h | RTI_CAUC0 | RTI Capture Up Counter 0 Register | 0E00 0024h | 0E01 0024h |
30h | RTI_FRC1 | RTI Free Running Counter 1 Register | 0E00 0030h | 0E01 0030h |
34h | RTI_UC1 | RTI Up Counter 1 Register | 0E00 0034h | 0E01 0034h |
38h | RTI_CPUC1 | RTI Compare Up Counter 1 Register | 0E00 0038h | 0E01 0038h |
40h | RTI_CAFRC1 | RTI Capture Free Running Counter 1 Register | 0E00 0040h | 0E01 0040h |
44h | RTI_CAUC1 | RTI Capture Up Counter 1 Register | 0E00 0044h | 0E01 0044h |
50h | RTI_COMP0 | RTI Compare 0 Register | 0E00 0050h | 0E01 0050h |
54h | RTI_UDCP0 | RTI Update Compare 0 Register | 0E00 0054h | 0E01 0054h |
58h | RTI_COMP1 | RTI Compare 1 Register | 0E00 0058h | 0E01 0058h |
5Ch | RTI_UDCP1 | RTI Update Compare 1 Register | 0E00 005Ch | 0E01 005Ch |
60h | RTI_COMP2 | RTI Compare 2 Register | 0E00 0060h | 0E01 0060h |
64h | RTI_UDCP2 | RTI Update Compare 2 Register | 0E00 0064h | 0E01 0064h |
68h | RTI_COMP3 | RTI Compare 3 Register | 0E00 0068h | 0E01 0068h |
6Ch | RTI_UDCP3 | RTI Update Compare 3 Register | 0E00 006Ch | 0E01 006Ch |
70h | RTI_TBLCOMP | RTI External Clock Timebase Low Compare Register | 0E00 0070h | 0E01 0070h |
74h | RTI_TBHCOMP | RTI External Clock Timebase High Compare Register | 0E00 0074h | 0E01 0074h |
80h | RTI_SETINT | RTI Set/Status Interrupt Register | 0E00 0080h | 0E01 0080h |
84h | RTI_CLEARINT | RTI Clear/Status Interrupt Register | 0E00 0084h | 0E01 0084h |
88h | RTI_INTFLAG | RTI Interrupt Flag Register | 0E00 0088h | 0E01 0088h |
90h | RTI_DWDCTRL | Digital Watchdog Control Register | 0E00 0090h | 0E01 0090h |
94h | RTI_DWDPRLD | Digital Watchdog Preload Register | 0E00 0094h | 0E01 0094h |
98h | RTI_WDSTATUS | Watchdog Status Register | 0E00 0098h | 0E01 0098h |
9Ch | RTI_WDKEY | Watchdog Key Register | 0E00 009Ch | 0E01 009Ch |
A0h | RTI_DWDCNTR | Digital Watchdog Down Counter | 0E00 00A0h | 0E01 00A0h |
A4h | RTI_WWDRXNCTRL | Digital Windowed Watchdog Reaction Control | 0E00 00A4h | 0E01 00A4h |
A8h | RTI_WWDSIZECTRL | Digital Windowed Watchdog Window Size Control | 0E00 00A8h | 0E01 00A8h |
ACh | RTI_INTCLRENABLE | RTI Compare Interrupt Clear Enable Register | 0E00 00ACh | 0E01 00ACh |
B0h | RTI_COMP0CLR | RTI Compare 0 Clear Register | 0E00 00B0h | 0E01 00B0h |
B4h | RTI_COMP1CLR | RTI Compare 1 Clear Register | 0E00 00B4h | 0E01 00B4h |
B8h | RTI_COMP2CLR | RTI Compare 2 Clear Register | 0E00 00B8h | 0E01 00B8h |
BCh | RTI_COMP3CLR | RTI Compare 3 Clear Register | 0E00 00BCh | 0E01 00BCh |
Offset | Acronym | Register Name | RTI8_CFG Physical Address | RTI9_CFG Physical Address |
---|---|---|---|---|
0h | RTI_GCTRL | RTI Global Control Register | 0E08 0000h | 0E09 0000h |
4h | RTI_TBCTRL | RTI Timebase Control Register | 0E08 0004h | 0E09 0004h |
8h | RTI_CAPCTRL | RTI Capture Control Register | 0E08 0008h | 0E09 0008h |
Ch | RTI_COMPCTRL | RTI Compare Control Register | 0E08 000Ch | 0E09 000Ch |
10h | RTI_FRC0 | RTI Free Running Counter 0 Register | 0E08 0010h | 0E09 0010h |
14h | RTI_UC0 | RTI Up Counter 0 Register | 0E08 0014h | 0E09 0014h |
18h | RTI_CPUC0 | RTI Compare Up Counter 0 Register | 0E08 0018h | 0E09 0018h |
20h | RTI_CAFRC0 | RTI Capture Free Running Counter 0 Register | 0E08 0020h | 0E09 0020h |
24h | RTI_CAUC0 | RTI Capture Up Counter 0 Register | 0E08 0024h | 0E09 0024h |
30h | RTI_FRC1 | RTI Free Running Counter 1 Register | 0E08 0030h | 0E09 0030h |
34h | RTI_UC1 | RTI Up Counter 1 Register | 0E08 0034h | 0E09 0034h |
38h | RTI_CPUC1 | RTI Compare Up Counter 1 Register | 0E08 0038h | 0E09 0038h |
40h | RTI_CAFRC1 | RTI Capture Free Running Counter 1 Register | 0E08 0040h | 0E09 0040h |
44h | RTI_CAUC1 | RTI Capture Up Counter 1 Register | 0E08 0044h | 0E09 0044h |
50h | RTI_COMP0 | RTI Compare 0 Register | 0E08 0050h | 0E09 0050h |
54h | RTI_UDCP0 | RTI Update Compare 0 Register | 0E08 0054h | 0E09 0054h |
58h | RTI_COMP1 | RTI Compare 1 Register | 0E08 0058h | 0E09 0058h |
5Ch | RTI_UDCP1 | RTI Update Compare 1 Register | 0E08 005Ch | 0E09 005Ch |
60h | RTI_COMP2 | RTI Compare 2 Register | 0E08 0060h | 0E09 0060h |
64h | RTI_UDCP2 | RTI Update Compare 2 Register | 0E08 0064h | 0E09 0064h |
68h | RTI_COMP3 | RTI Compare 3 Register | 0E08 0068h | 0E09 0068h |
6Ch | RTI_UDCP3 | RTI Update Compare 3 Register | 0E08 006Ch | 0E09 006Ch |
70h | RTI_TBLCOMP | RTI External Clock Timebase Low Compare Register | 0E08 0070h | 0E09 0070h |
74h | RTI_TBHCOMP | RTI External Clock Timebase High Compare Register | 0E08 0074h | 0E09 0074h |
80h | RTI_SETINT | RTI Set/Status Interrupt Register | 0E08 0080h | 0E09 0080h |
84h | RTI_CLEARINT | RTI Clear/Status Interrupt Register | 0E08 0084h | 0E09 0084h |
88h | RTI_INTFLAG | RTI Interrupt Flag Register | 0E08 0088h | 0E09 0088h |
90h | RTI_DWDCTRL | Digital Watchdog Control Register | 0E08 0090h | 0E09 0090h |
94h | RTI_DWDPRLD | Digital Watchdog Preload Register | 0E08 0094h | 0E09 0094h |
98h | RTI_WDSTATUS | Watchdog Status Register | 0E08 0098h | 0E09 0098h |
9Ch | RTI_WDKEY | Watchdog Key Register | 0E08 009Ch | 0E09 009Ch |
A0h | RTI_DWDCNTR | Digital Watchdog Down Counter | 0E08 00A0h | 0E09 00A0h |
A4h | RTI_WWDRXNCTRL | Digital Windowed Watchdog Reaction Control | 0E08 00A4h | 0E09 00A4h |
A8h | RTI_WWDSIZECTRL | Digital Windowed Watchdog Window Size Control | 0E08 00A8h | 0E09 00A8h |
ACh | RTI_INTCLRENABLE | RTI Compare Interrupt Clear Enable Register | 0E08 00ACh | 0E09 00ACh |
B0h | RTI_COMP0CLR | RTI Compare 0 Clear Register | 0E08 00B0h | 0E09 00B0h |
B4h | RTI_COMP1CLR | RTI Compare 1 Clear Register | 0E08 00B4h | 0E09 00B4h |
B8h | RTI_COMP2CLR | RTI Compare 2 Clear Register | 0E08 00B8h | 0E09 00B8h |
BCh | RTI_COMP3CLR | RTI Compare 3 Clear Register | 0E08 00BCh | 0E09 00BCh |
Offset | Acronym | Register Name | RTI10_CFG Physical Address | RTI11_CFG Physical Address |
---|---|---|---|---|
0h | RTI_GCTRL | RTI Global Control Register | 0E0A 0000h | 0E0B 0000h |
4h | RTI_TBCTRL | RTI Timebase Control Register | 0E0A 0004h | 0E0B 0004h |
8h | RTI_CAPCTRL | RTI Capture Control Register | 0E0A 0008h | 0E0B 0008h |
Ch | RTI_COMPCTRL | RTI Compare Control Register | 0E0A 000Ch | 0E0B 000Ch |
10h | RTI_FRC0 | RTI Free Running Counter 0 Register | 0E0A 0010h | 0E0B 0010h |
14h | RTI_UC0 | RTI Up Counter 0 Register | 0E0A 0014h | 0E0B 0014h |
18h | RTI_CPUC0 | RTI Compare Up Counter 0 Register | 0E0A 0018h | 0E0B 0018h |
20h | RTI_CAFRC0 | RTI Capture Free Running Counter 0 Register | 0E0A 0020h | 0E0B 0020h |
24h | RTI_CAUC0 | RTI Capture Up Counter 0 Register | 0E0A 0024h | 0E0B 0024h |
30h | RTI_FRC1 | RTI Free Running Counter 1 Register | 0E0A 0030h | 0E0B 0030h |
34h | RTI_UC1 | RTI Up Counter 1 Register | 0E0A 0034h | 0E0B 0034h |
38h | RTI_CPUC1 | RTI Compare Up Counter 1 Register | 0E0A 0038h | 0E0B 0038h |
40h | RTI_CAFRC1 | RTI Capture Free Running Counter 1 Register | 0E0A 0040h | 0E0B 0040h |
44h | RTI_CAUC1 | RTI Capture Up Counter 1 Register | 0E0A 0044h | 0E0B 0044h |
50h | RTI_COMP0 | RTI Compare 0 Register | 0E0A 0050h | 0E0B 0050h |
54h | RTI_UDCP0 | RTI Update Compare 0 Register | 0E0A 0054h | 0E0B 0054h |
58h | RTI_COMP1 | RTI Compare 1 Register | 0E0A 0058h | 0E0B 0058h |
5Ch | RTI_UDCP1 | RTI Update Compare 1 Register | 0E0A 005Ch | 0E0B 005Ch |
60h | RTI_COMP2 | RTI Compare 2 Register | 0E0A 0060h | 0E0B 0060h |
64h | RTI_UDCP2 | RTI Update Compare 2 Register | 0E0A 0064h | 0E0B 0064h |
68h | RTI_COMP3 | RTI Compare 3 Register | 0E0A 0068h | 0E0B 0068h |
6Ch | RTI_UDCP3 | RTI Update Compare 3 Register | 0E0A 006Ch | 0E0B 006Ch |
70h | RTI_TBLCOMP | RTI External Clock Timebase Low Compare Register | 0E0A 0070h | 0E0B 0070h |
74h | RTI_TBHCOMP | RTI External Clock Timebase High Compare Register | 0E0A 0074h | 0E0B 0074h |
80h | RTI_SETINT | RTI Set/Status Interrupt Register | 0E0A 0080h | 0E0B 0080h |
84h | RTI_CLEARINT | RTI Clear/Status Interrupt Register | 0E0A 0084h | 0E0B 0084h |
88h | RTI_INTFLAG | RTI Interrupt Flag Register | 0E0A 0088h | 0E0B 0088h |
90h | RTI_DWDCTRL | Digital Watchdog Control Register | 0E0A 0090h | 0E0B 0090h |
94h | RTI_DWDPRLD | Digital Watchdog Preload Register | 0E0A 0094h | 0E0B 0094h |
98h | RTI_WDSTATUS | Watchdog Status Register | 0E0A 0098h | 0E0B 0098h |
9Ch | RTI_WDKEY | Watchdog Key Register | 0E0A 009Ch | 0E0B 009Ch |
A0h | RTI_DWDCNTR | Digital Watchdog Down Counter | 0E0A 00A0h | 0E0B 00A0h |
A4h | RTI_WWDRXNCTRL | Digital Windowed Watchdog Reaction Control | 0E0A 00A4h | 0E0B 00A4h |
A8h | RTI_WWDSIZECTRL | Digital Windowed Watchdog Window Size Control | 0E0A 00A8h | 0E0B 00A8h |
ACh | RTI_INTCLRENABLE | RTI Compare Interrupt Clear Enable Register | 0E0A 00ACh | 0E0B 00ACh |
B0h | RTI_COMP0CLR | RTI Compare 0 Clear Register | 0E0A 00B0h | 0E0B 00B0h |
B4h | RTI_COMP1CLR | RTI Compare 1 Clear Register | 0E0A 00B4h | 0E0B 00B4h |
B8h | RTI_COMP2CLR | RTI Compare 2 Clear Register | 0E0A 00B8h | 0E0B 00B8h |
BCh | RTI_COMP3CLR | RTI Compare 3 Clear Register | 0E0A 00BCh | 0E0B 00BCh |
Offset | Acronym | Register Name | MCU_RTI0_CFG Physical Address |
---|---|---|---|
0h | RTI_GCTRL | RTI Global Control Register | 0488 0000h |
4h | RTI_TBCTRL | RTI Timebase Control Register | 0488 0004h |
8h | RTI_CAPCTRL | RTI Capture Control Register | 0488 0008h |
Ch | RTI_COMPCTRL | RTI Compare Control Register | 0488 000Ch |
10h | RTI_FRC0 | RTI Free Running Counter 0 Register | 0488 0010h |
14h | RTI_UC0 | RTI Up Counter 0 Register | 0488 0014h |
18h | RTI_CPUC0 | RTI Compare Up Counter 0 Register | 0488 0018h |
20h | RTI_CAFRC0 | RTI Capture Free Running Counter 0 Register | 0488 0020h |
24h | RTI_CAUC0 | RTI Capture Up Counter 0 Register | 0488 0024h |
30h | RTI_FRC1 | RTI Free Running Counter 1 Register | 0488 0030h |
34h | RTI_UC1 | RTI Up Counter 1 Register | 0488 0034h |
38h | RTI_CPUC1 | RTI Compare Up Counter 1 Register | 0488 0038h |
40h | RTI_CAFRC1 | RTI Capture Free Running Counter 1 Register | 0488 0040h |
44h | RTI_CAUC1 | RTI Capture Up Counter 1 Register | 0488 0044h |
50h | RTI_COMP0 | RTI Compare 0 Register | 0488 0050h |
54h | RTI_UDCP0 | RTI Update Compare 0 Register | 0488 0054h |
58h | RTI_COMP1 | RTI Compare 1 Register | 0488 0058h |
5Ch | RTI_UDCP1 | RTI Update Compare 1 Register | 0488 005Ch |
60h | RTI_COMP2 | RTI Compare 2 Register | 0488 0060h |
64h | RTI_UDCP2 | RTI Update Compare 2 Register | 0488 0064h |
68h | RTI_COMP3 | RTI Compare 3 Register | 0488 0068h |
6Ch | RTI_UDCP3 | RTI Update Compare 3 Register | 0488 006Ch |
70h | RTI_TBLCOMP | RTI External Clock Timebase Low Compare Register | 0488 0070h |
74h | RTI_TBHCOMP | RTI External Clock Timebase High Compare Register | 0488 0074h |
80h | RTI_SETINT | RTI Set/Status Interrupt Register | 0488 0080h |
84h | RTI_CLEARINT | RTI Clear/Status Interrupt Register | 0488 0084h |
88h | RTI_INTFLAG | RTI Interrupt Flag Register | 0488 0088h |
90h | RTI_DWDCTRL | Digital Watchdog Control Register | 0488 0090h |
94h | RTI_DWDPRLD | Digital Watchdog Preload Register | 0488 0094h |
98h | RTI_WDSTATUS | Watchdog Status Register | 0488 0098h |
9Ch | RTI_WDKEY | Watchdog Key Register | 0488 009Ch |
A0h | RTI_DWDCNTR | Digital Watchdog Down Counter | 0488 00A0h |
A4h | RTI_WWDRXNCTRL | Digital Windowed Watchdog Reaction Control | 0488 00A4h |
A8h | RTI_WWDSIZECTRL | Digital Windowed Watchdog Window Size Control | 0488 00A8h |
ACh | RTI_INTCLRENABLE | RTI Compare Interrupt Clear Enable Register | 0488 00ACh |
B0h | RTI_COMP0CLR | RTI Compare 0 Clear Register | 0488 00B0h |
B4h | RTI_COMP1CLR | RTI Compare 1 Clear Register | 0488 00B4h |
B8h | RTI_COMP2CLR | RTI Compare 2 Clear Register | 0488 00B8h |
BCh | RTI_COMP3CLR | RTI Compare 3 Clear Register | 0488 00BCh |
RTI_GCTRL is shown in Figure 12-2430 and described in Table 12-4630.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0000h |
RTI1_CFG | 0E01 0000h |
RTI8_CFG | 0E08 0000h |
RTI9_CFG | 0E09 0000h |
RTI10_CFG | 0E0A 0000h |
RTI11_CFG | 0E0B 0000h |
MCU_RTI0_CFG | 0488 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
COS | RESERVED | ||||||
R/W-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNT1EN | CNT0EN | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | RESERVED | R | 0h | Reserved |
15 | COS | R/W | 0h | Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. |
14-2 | RESERVED | R | 0h | Reserved. |
1 | CNT1EN | R/W | 0h | Counter 1 Enable. |
0 | CNT0EN | R/W | 0h | Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0). |
RTI_TBCTRL is shown in Figure 12-2431 and described in Table 12-4632.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0004h |
RTI1_CFG | 0E01 0004h |
RTI8_CFG | 0E08 0004h |
RTI9_CFG | 0E09 0004h |
RTI10_CFG | 0E0A 0004h |
RTI11_CFG | 0E0B 0004h |
MCU_RTI0_CFG | 0488 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INC | TBEXT | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | INC | R/W | 0h | This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. |
0 | TBEXT | R/W | 0h | The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. |
RTI_CAPCTRL is shown in Figure 12-2432 and described in Table 12-4634.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0008h |
RTI1_CFG | 0E01 0008h |
RTI8_CFG | 0E08 0008h |
RTI9_CFG | 0E09 0008h |
RTI10_CFG | 0E0A 0008h |
RTI11_CFG | 0E0B 0008h |
MCU_RTI0_CFG | 0488 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAPCNTR1 | CAPCNTR0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CAPCNTR1 | R/W | 0h | Capture Counter 1. |
0 | CAPCNTR0 | R/W | 0h | Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. |
RTI_COMPCTRL is shown in Figure 12-2433 and described in Table 12-4636.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 000Ch |
RTI1_CFG | 0E01 000Ch |
RTI8_CFG | 0E08 000Ch |
RTI9_CFG | 0E09 000Ch |
RTI10_CFG | 0E0A 000Ch |
RTI11_CFG | 0E0B 000Ch |
MCU_RTI0_CFG | 0488 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COMPSEL3 | RESERVED | COMPSEL2 | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMPSEL1 | RESERVED | COMPSEL0 | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12 | COMPSEL3 | R/W | 0h | Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. |
11-9 | RESERVED | R | 0h | Reserved |
8 | COMPSEL2 | R/W | 0h | Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. |
7-5 | RESERVED | R | 0h | Reserved |
4 | COMPSEL1 | R/W | 0h | Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. |
3-1 | RESERVED | R | 0h | Reserved |
0 | COMPSEL0 | R/W | 0h | Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. |
RTI_FRC0 is shown in Figure 12-2434 and described in Table 12-4638.
Return to Summary Table.
This registers holds the current value of the Free Running Counter 0 and will be updated continuously.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0010h |
RTI1_CFG | 0E01 0010h |
RTI8_CFG | 0E08 0010h |
RTI9_CFG | 0E09 0010h |
RTI10_CFG | 0E0A 0010h |
RTI11_CFG | 0E0B 0010h |
MCU_RTI0_CFG | 0488 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRC0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FRC0 | R/W | 0h | Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. |
RTI_UC0 is shown in Figure 12-2435 and described in Table 12-4640.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0014h |
RTI1_CFG | 0E01 0014h |
RTI8_CFG | 0E08 0014h |
RTI9_CFG | 0E09 0014h |
RTI10_CFG | 0E0A 0014h |
RTI11_CFG | 0E0B 0014h |
MCU_RTI0_CFG | 0488 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UC0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UC0 | R/W | 0h | Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. |
RTI_CPUC0 is shown in Figure 12-2436 and described in Table 12-4642.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0018h |
RTI1_CFG | 0E01 0018h |
RTI8_CFG | 0E08 0018h |
RTI9_CFG | 0E09 0018h |
RTI10_CFG | 0E0A 0018h |
RTI11_CFG | 0E0B 0018h |
MCU_RTI0_CFG | 0488 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPUC0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CPUC0 | R/W | 0h | Compare Up Counter 0. This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI. |
RTI_CAFRC0 is shown in Figure 12-2437 and described in Table 12-4644.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0020h |
RTI1_CFG | 0E01 0020h |
RTI8_CFG | 0E08 0020h |
RTI9_CFG | 0E09 0020h |
RTI10_CFG | 0E0A 0020h |
RTI11_CFG | 0E0B 0020h |
MCU_RTI0_CFG | 0488 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAFRC0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAFRC0 | R | 0h | Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when an event occurs, controlled by the external capture control block. |
RTI_CAUC0 is shown in Figure 12-2438 and described in Table 12-4646.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0024h |
RTI1_CFG | 0E01 0024h |
RTI8_CFG | 0E08 0024h |
RTI9_CFG | 0E09 0024h |
RTI10_CFG | 0E0A 0024h |
RTI11_CFG | 0E0B 0024h |
MCU_RTI0_CFG | 0488 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAUC0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAUC0 | R | 0h | Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when an event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTI_CAFRC0 register has to be read first, before the RTI_CAUC0 register is read. This sequence ensures that the value of the RTI_CAUC0 register is the corresponding value to the RTI_CAFRC0 register, even if another capture event happens in between the two reads. |
RTI_FRC1 is shown in Figure 12-2439 and described in Table 12-4648.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0030h |
RTI1_CFG | 0E01 0030h |
RTI8_CFG | 0E08 0030h |
RTI9_CFG | 0E09 0030h |
RTI10_CFG | 0E0A 0030h |
RTI11_CFG | 0E0B 0030h |
MCU_RTI0_CFG | 0488 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRC1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FRC1 | R/W | 0h | Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. |
RTI_UC1 is shown in Figure 12-2440 and described in Table 12-4650.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0034h |
RTI1_CFG | 0E01 0034h |
RTI8_CFG | 0E08 0034h |
RTI9_CFG | 0E09 0034h |
RTI10_CFG | 0E0A 0034h |
RTI11_CFG | 0E0B 0034h |
MCU_RTI0_CFG | 0488 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UC1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UC1 | R/W | 0h | Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. |
RTI_CPUC1 is shown in Figure 12-2441 and described in Table 12-4652.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0038h |
RTI1_CFG | 0E01 0038h |
RTI8_CFG | 0E08 0038h |
RTI9_CFG | 0E09 0038h |
RTI10_CFG | 0E0A 0038h |
RTI11_CFG | 0E0B 0038h |
MCU_RTI0_CFG | 0488 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPUC1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CPUC1 | R/W | 0h | Compare Up Counter 1. This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI. |
RTI_CAFRC1 is shown in Figure 12-2442 and described in Table 12-4654.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0040h |
RTI1_CFG | 0E01 0040h |
RTI8_CFG | 0E08 0040h |
RTI9_CFG | 0E09 0040h |
RTI10_CFG | 0E0A 0040h |
RTI11_CFG | 0E0B 0040h |
MCU_RTI0_CFG | 0488 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAFRC1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAFRC1 | R | 0h | Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when an event occurs, controlled by the external capture control block. |
RTI_CAUC1 is shown in Figure 12-2443 and described in Table 12-4656.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0044h |
RTI1_CFG | 0E01 0044h |
RTI8_CFG | 0E08 0044h |
RTI9_CFG | 0E09 0044h |
RTI10_CFG | 0E0A 0044h |
RTI11_CFG | 0E0B 0044h |
MCU_RTI0_CFG | 0488 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAUC1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAUC1 | R | 0h | Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when an event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTI_CAFRC1 register has to be read first, before the RTI_CAUC1 register is read. This sequence ensures that the value of the RTI_CAUC0 register is the corresponding value to the RTI_CAFRC0 register, even if another capture event happens in between the two reads. |
RTI_COMP0 is shown in Figure 12-2444 and described in Table 12-4658.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0050h |
RTI1_CFG | 0E01 0050h |
RTI8_CFG | 0E08 0050h |
RTI9_CFG | 0E09 0050h |
RTI10_CFG | 0E0A 0050h |
RTI11_CFG | 0E0B 0050h |
MCU_RTI0_CFG | 0488 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP0 | R/W | 0h | Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. |
RTI_UDCP0 is shown in Figure 12-2445 and described in Table 12-4660.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0054h |
RTI1_CFG | 0E01 0054h |
RTI8_CFG | 0E08 0054h |
RTI9_CFG | 0E09 0054h |
RTI10_CFG | 0E0A 0054h |
RTI11_CFG | 0E0B 0054h |
MCU_RTI0_CFG | 0488 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDCP0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UDCP0 | R/W | 0h | Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. |
RTI_COMP1 is shown in Figure 12-2446 and described in Table 12-4662.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0058h |
RTI1_CFG | 0E01 0058h |
RTI8_CFG | 0E08 0058h |
RTI9_CFG | 0E09 0058h |
RTI10_CFG | 0E0A 0058h |
RTI11_CFG | 0E0B 0058h |
MCU_RTI0_CFG | 0488 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP1 | R/W | 0h | Compare 1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. |
RTI_UDCP1 is shown in Figure 12-2447 and described in Table 12-4664.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 005Ch |
RTI1_CFG | 0E01 005Ch |
RTI8_CFG | 0E08 005Ch |
RTI9_CFG | 0E09 005Ch |
RTI10_CFG | 0E0A 005Ch |
RTI11_CFG | 0E0B 005Ch |
MCU_RTI0_CFG | 0488 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDCP1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UDCP1 | R/W | 0h | Update Compare 1 Register. This registers holds a value, which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. |
RTI_COMP2 is shown in Figure 12-2448 and described in Table 12-4666.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0060h |
RTI1_CFG | 0E01 0060h |
RTI8_CFG | 0E08 0060h |
RTI9_CFG | 0E09 0060h |
RTI10_CFG | 0E0A 0060h |
RTI11_CFG | 0E0B 0060h |
MCU_RTI0_CFG | 0488 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP2 | R/W | 0h | Compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. |
RTI_UDCP2 is shown in Figure 12-2449 and described in Table 12-4668.
Return to Summary Table.
This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0064h |
RTI1_CFG | 0E01 0064h |
RTI8_CFG | 0E08 0064h |
RTI9_CFG | 0E09 0064h |
RTI10_CFG | 0E0A 0064h |
RTI11_CFG | 0E0B 0064h |
MCU_RTI0_CFG | 0488 0064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDCP2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UDCP2 | R/W | 0h | Update Compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. |
RTI_COMP3 is shown in Figure 12-2450 and described in Table 12-4670.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0068h |
RTI1_CFG | 0E01 0068h |
RTI8_CFG | 0E08 0068h |
RTI9_CFG | 0E09 0068h |
RTI10_CFG | 0E0A 0068h |
RTI11_CFG | 0E0B 0068h |
MCU_RTI0_CFG | 0488 0068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP3 | R/W | 0h | Compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. |
RTI_UDCP3 is shown in Figure 12-2451 and described in Table 12-4672.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 006Ch |
RTI1_CFG | 0E01 006Ch |
RTI8_CFG | 0E08 006Ch |
RTI9_CFG | 0E09 006Ch |
RTI10_CFG | 0E0A 006Ch |
RTI11_CFG | 0E0B 006Ch |
MCU_RTI0_CFG | 0488 006Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDCP3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UDCP3 | R/W | 0h | Update Compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. |
RTI_TBLCOMP is shown in Figure 12-2452 and described in Table 12-4674.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0070h |
RTI1_CFG | 0E01 0070h |
RTI8_CFG | 0E08 0070h |
RTI9_CFG | 0E09 0070h |
RTI10_CFG | 0E0A 0070h |
RTI11_CFG | 0E0B 0070h |
MCU_RTI0_CFG | 0488 0070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBLCOMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TBLCOMP | R | 0h | Reserved |
RTI_TBHCOMP is shown in Figure 12-2453 and described in Table 12-4676.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0074h |
RTI1_CFG | 0E01 0074h |
RTI8_CFG | 0E08 0074h |
RTI9_CFG | 0E09 0074h |
RTI10_CFG | 0E0A 0074h |
RTI11_CFG | 0E0B 0074h |
MCU_RTI0_CFG | 0488 0074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBHCOMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TBHCOMP | R | 0h | Reserved |
RTI_SETINT is shown in Figure 12-2454 and described in Table 12-4678.
Return to Summary Table.
This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see Section 12.5.2.1.2, RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0080h |
RTI1_CFG | 0E01 0080h |
RTI8_CFG | 0E08 0080h |
RTI9_CFG | 0E09 0080h |
RTI10_CFG | 0E0A 0080h |
RTI11_CFG | 0E0B 0080h |
MCU_RTI0_CFG | 0488 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SETOVL1INT | SETOVL0INT | SETTBINT | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SETDMA3 | SETDMA2 | SETDMA1 | SETDMA0 | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SETINT3 | SETINT2 | SETINT1 | SETINT0 | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18 | SETOVL1INT | R/W1S | 0h | Set Free Running Counter 1 Overflow Interrupt. |
17 | SETOVL0INT | R/W1S | 0h | Set Free Running Counter 0 Overflow Interrupt. |
16 | SETTBINT | R/W1S | 0h |
User and privilege mode (read): |
15-12 | RESERVED | R | 0h | Reserved |
11 | SETDMA3 | R/W1S | 0h | Set Compare DMA Request 3. |
10 | SETDMA2 | R/W1S | 0h | Set Compare DMA Request 2. |
9 | SETDMA1 | R/W1S | 0h | Set Compare DMA Request 1. |
8 | SETDMA0 | R/W1S | 0h | Set Compare DMA Request 0. |
7-4 | RESERVED | R | 0h | Reserved |
3 | SETINT3 | R/W1S | 0h | Set Compare Interrupt 3. |
2 | SETINT2 | R/W1S | 0h | Set Compare Interrupt 2. |
1 | SETINT1 | R/W1S | 0h | Set Compare Interrupt 1. |
0 | SETINT0 | R/W1S | 0h | Set Compare Interrupt 0. |
RTI_CLEARINT is shown in Figure 12-2455 and described in Table 12-4680.
Return to Summary Table.
This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see Section 12.5.2.1.2, RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0084h |
RTI1_CFG | 0E01 0084h |
RTI8_CFG | 0E08 0084h |
RTI9_CFG | 0E09 0084h |
RTI10_CFG | 0E0A 0084h |
RTI11_CFG | 0E0B 0084h |
MCU_RTI0_CFG | 0488 0084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CLEAROVL1INT | CLEAROVL0INT | CLEARTBINT | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLEARDMA3 | CLEARDMA2 | CLEARDMA1 | CLEARDMA0 | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLEARINT3 | CLEARINT2 | CLEARINT1 | CLEARINT0 | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18 | CLEAROVL1INT | R/W1C | 0h | Clear Free Running Counter 1 Overflow Interrupt. |
17 | CLEAROVL0INT | R/W1C | 0h | Clear Free Running Counter 0 Overflow Interrupt. |
16 | CLEARTBINT | R/W1C | 0h |
|
15-12 | RESERVED | R | 0h | Reserved |
11 | CLEARDMA3 | R/W1C | 0h | Clear Compare DMA Request 3. |
10 | CLEARDMA2 | R/W1C | 0h | Clear Compare DMA Request 2. |
9 | CLEARDMA1 | R/W1C | 0h | Clear Compare DMA Request 1. |
8 | CLEARDMA0 | R/W1C | 0h | Clear Compare DMA Request 0. |
7-4 | RESERVED | R | 0h | Reserved |
3 | CLEARINT3 | R/W1C | 0h | Clear Compare Interrupt 3. |
2 | CLEARINT2 | R/W1C | 0h | Clear Compare Interrupt 2. |
1 | CLEARINT1 | R/W1C | 0h | Clear Compare Interrupt 1. |
0 | CLEARINT0 | R/W1C | 0h | Clear Compare Interrupt 0. |
RTI_INTFLAG is shown in Figure 12-2456 and described in Table 12-4682.
Return to Summary Table.
The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value, regardless if the interrupt is enabled or not.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0088h |
RTI1_CFG | 0E01 0088h |
RTI8_CFG | 0E08 0088h |
RTI9_CFG | 0E09 0088h |
RTI10_CFG | 0E0A 0088h |
RTI11_CFG | 0E0B 0088h |
MCU_RTI0_CFG | 0488 0088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | OVL1INT | OVL0INT | TBINT | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT3 | INT2 | INT1 | INT0 | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18 | OVL1INT | R/W1C | 0h | Free Running Counter 1 Overflow Interrupt Flag. |
17 | OVL0INT | R/W1C | 0h | Free Running Counter 0 Overflow Interrupt Flag. |
16 | TBINT | R/W1C | 0h | User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. |
15-4 | RESERVED | R | 0h | Reserved |
3 | INT3 | R/W1C | 0h | Interrupt Flag 3. |
2 | INT2 | R/W1C | 0h | Interrupt Flag 2. |
1 | INT1 | R/W1C | 0h | Interrupt Flag 1. |
0 | INT0 | R/W1C | 0h | Interrupt Flag 0. |
RTI_DWDCTRL is shown in Figure 12-2457 and described in Table 12-4684.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see Section 12.5.2.1.2, RTI Not Supported Features.
This register's functionality is dependent on whether the DWD is implemented to be always enabled or not. If the DWD is always enabled, then the DWD is automatically enabled after system reset is released and cannot be disabled by software. In that case, this register is redundant and any writes to this register have no effect on the DWD functionality. If, however, the DWD is not enabled upon release of system reset, then the software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once enabled, the watchdog can only be disabled by a system reset. The application cannot disable the watchdog. The RTI_DWDCTRL register also implements a one-time-write constraint. That is, once the application writes to this register to enable the watchdog, all further writes are ignored.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0090h |
RTI1_CFG | 0E01 0090h |
RTI8_CFG | 0E08 0090h |
RTI9_CFG | 0E09 0090h |
RTI10_CFG | 0E0A 0090h |
RTI11_CFG | 0E0B 0090h |
MCU_RTI0_CFG | 0488 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DWDCTRL | |||||||||||||||||||||||||||||||
R/W-5312ACEDh | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DWDCTRL | R/W | 5312ACEDh | Digital Watchdog Control. |
RTI_DWDPRLD is shown in Figure 12-2458 and described in Table 12-4686.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see Section 12.5.2.1.2, RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0094h |
RTI1_CFG | 0E01 0094h |
RTI8_CFG | 0E08 0094h |
RTI9_CFG | 0E09 0094h |
RTI10_CFG | 0E0A 0094h |
RTI11_CFG | 0E0B 0094h |
MCU_RTI0_CFG | 0488 0094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DWDPRLD | ||||||||||||||||||||||||||||||
R-0h | R/W-FFFh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-0 | DWDPRLD | R/W | FFFh | Digital Watchdog Preload Value. |
RTI_WDSTATUS is shown in Figure 12-2459 and described in Table 12-4688.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see Section 12.5.2.1.2, RTI Not Supported Features.
The values of the following status bits will not be affected by a system reset. These bits are cleared by a power up reset, or by the application.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 0098h |
RTI1_CFG | 0E01 0098h |
RTI8_CFG | 0E08 0098h |
RTI9_CFG | 0E09 0098h |
RTI10_CFG | 0E0A 0098h |
RTI11_CFG | 0E0B 0098h |
MCU_RTI0_CFG | 0488 0098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DWWD_ST | END | START | KEYST | DWDST | AWDST | |
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | DWWD_ST | R/W1C | 0h | Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. |
4 | END | R/W1C | 0h | Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. |
3 | START | R/W1C | 0h | Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. |
2 | KEYST | R/W1C | 0h | Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTI_WDKEY register. |
1 | DWDST | R/W1C | 0h | Digital Watchdog Status. Status flag and is maintained for compatibility reasons. |
0 | AWDST | R/W1C | 0h | Analog Watchdog Status. |
RTI_WDKEY is shown in Figure 12-2460 and described in Table 12-4690.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see Section 12.5.2.1.2, RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 009Ch |
RTI1_CFG | 0E01 009Ch |
RTI8_CFG | 0E08 009Ch |
RTI9_CFG | 0E09 009Ch |
RTI10_CFG | 0E0A 009Ch |
RTI11_CFG | 0E0B 009Ch |
MCU_RTI0_CFG | 0488 009Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDKEY | ||||||||||||||||||||||||||||||
R-0h | R/W-A35Ch | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description | ||
---|---|---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved | ||
15-0 | WDKEY | R/W | A35Ch | Watchdog Key. Example of a WDKEY sequence Step -> Value written to WDKEY -> Result 1 -> 0x0A35C -> No Action 2 -> 0x0A35C -> No Action 3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 4 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 5 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 6 -> 0x0A35C -> Watchdog is reset 7 -> 0x0A35C -> No Action 8 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 9 -> 0x0A35C -> Watchdog is reset 10 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 11 -> 0x02345 -> System reset; incorrect value written to WDKEY |
RTI_DWDCNTR is shown in Figure 12-2461 and described in Table 12-4692.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see Section 12.5.2.1.2, RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 00A0h |
RTI1_CFG | 0E01 00A0h |
RTI8_CFG | 0E08 00A0h |
RTI9_CFG | 0E09 00A0h |
RTI10_CFG | 0E0A 00A0h |
RTI11_CFG | 0E0B 00A0h |
MCU_RTI0_CFG | 0488 00A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DWDCNTR | ||||||||||||||
R-0h | R-01FFFFFFh | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DWDCNTR | |||||||||||||||
R-01FFFFFFh | |||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24-0 | DWDCNTR | R | 01FFFFFFh | Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 01FFFFFFh. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3 MHz, a watchdog reset will be generated in 1 second. |
RTI_WWDRXNCTRL is shown in Figure 12-2462 and described in Table 12-4694.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 00A4h |
RTI1_CFG | 0E01 00A4h |
RTI8_CFG | 0E08 00A4h |
RTI9_CFG | 0E09 00A4h |
RTI10_CFG | 0E0A 00A4h |
RTI11_CFG | 0E0B 00A4h |
MCU_RTI0_CFG | 0488 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WWDRXN | ||||||||||||||
R-0h | R/W-5h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | WWDRXN | R/W | 5h | Digital Windowed Watchdog Reaction. |
RTI_WWDSIZECTRL is shown in Figure 12-2463 and described in Table 12-4696.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 00A8h |
RTI1_CFG | 0E01 00A8h |
RTI8_CFG | 0E08 00A8h |
RTI9_CFG | 0E09 00A8h |
RTI10_CFG | 0E0A 00A8h |
RTI11_CFG | 0E0B 00A8h |
MCU_RTI0_CFG | 0488 00A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WWDSIZE | |||||||||||||||||||||||||||||||
R/W-5h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WWDSIZE | R/W | 5h | Digital Windowed Watchdog Window Size. |
RTI_INTCLRENABLE is shown in Figure 12-2464 and described in Table 12-4698.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 00ACh |
RTI1_CFG | 0E01 00ACh |
RTI8_CFG | 0E08 00ACh |
RTI9_CFG | 0E09 00ACh |
RTI10_CFG | 0E0A 00ACh |
RTI11_CFG | 0E0B 00ACh |
MCU_RTI0_CFG | 0488 00ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | INTCLRENABLE3 | ||||||
R-0h | R/W-5h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | INTCLRENABLE2 | ||||||
R-0h | R/W-5h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INTCLRENABLE1 | ||||||
R-0h | R/W-5h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTCLRENABLE0 | ||||||
R-0h | R/W-5h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-24 | INTCLRENABLE3 | R/W | 5h | Enables the auto-clear functionality on the compare 3 interrupt. |
23-20 | RESERVED | R | 0h | Reserved |
19-16 | INTCLRENABLE2 | R/W | 5h | Enables the auto-clear functionality on the compare 2 interrupt. |
15-12 | RESERVED | R | 0h | Reserved |
11-8 | INTCLRENABLE1 | R/W | 5h | Enables the auto-clear functionality on the compare 1 interrupt. |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | INTCLRENABLE0 | R/W | 5h | Enables the auto-clear functionality on the compare 0 interrupt. |
RTI_COMP0CLR is shown in Figure 12-2465 and described in Table 12-4700.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 00B0h |
RTI1_CFG | 0E01 00B0h |
RTI8_CFG | 0E08 00B0h |
RTI9_CFG | 0E09 00B0h |
RTI10_CFG | 0E0A 00B0h |
RTI11_CFG | 0E0B 00B0h |
MCU_RTI0_CFG | 0488 00B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP0CLR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP0CLR | R/W | 0h | Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. |
RTI_COMP1CLR is shown in Figure 12-2466 and described in Table 12-4702.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 00B4h |
RTI1_CFG | 0E01 00B4h |
RTI8_CFG | 0E08 00B4h |
RTI9_CFG | 0E09 00B4h |
RTI10_CFG | 0E0A 00B4h |
RTI11_CFG | 0E0B 00B4h |
MCU_RTI0_CFG | 0488 00B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP1CLR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP1CLR | R/W | 0h | Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 1 interrupt or DMA request line is cleared. |
RTI_COMP2CLR is shown in Figure 12-2467 and described in Table 12-4704.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 00B8h |
RTI1_CFG | 0E01 00B8h |
RTI8_CFG | 0E08 00B8h |
RTI9_CFG | 0E09 00B8h |
RTI10_CFG | 0E0A 00B8h |
RTI11_CFG | 0E0B 00B8h |
MCU_RTI0_CFG | 0488 00B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP2CLR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP2CLR | R/W | 0h | Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 2 interrupt or DMA request line is cleared. |
RTI_COMP3CLR is shown in Figure 12-2468 and described in Table 12-4706.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0E00 00BCh |
RTI1_CFG | 0E01 00BCh |
RTI8_CFG | 0E08 00BCh |
RTI9_CFG | 0E09 00BCh |
RTI10_CFG | 0E0A 00BCh |
RTI11_CFG | 0E0B 00BCh |
MCU_RTI0_CFG | 0488 00BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP3CLR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP3CLR | R/W | 0h | Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 3 interrupt or DMA request line is cleared. |