SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes module integration in the device, including information about clocks, resets, and hardware requests.
Figure 7-15 shows the Spinlock integration.
Table 7-41 and Table 7-42 summarize the integration of the module in the device.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
SPINLOCK0 | PSC0 | GP | LPSC0 | INFRA_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
SPINLOCK0 | SPINLOCK0_VBUS_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | Spinlock clock. This clock is used for all interface and functional operations. |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
SPINLOCK0 | SPINLOCK0_RST | MOD_G_RST | LPSC0 | Spinlock hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
SPINLOCK0 | - | - | - | No interrupts to external processors | - |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
SPINLOCK0 | - | - | - | No PDMA channels to external DMA engines | - |