SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-252 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 12-252 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
I2C0_CFG | 2000 0000h |
I2C1_CFG | 2001 0000h |
I2C2_CFG | 2002 0000h |
I2C3_CFG | 2003 0000h |
MCU_I2C0_CFG | 0490 0000h |
MCU_I2C1_CFG | 0491 0000h |
Offset | Acronym | Register Name | I2C0_CFG Physical Address | I2C1_CFG Physical Address | I2C2_CFG Physical Address |
---|---|---|---|---|---|
0h | I2C_REVNB_LO | 2000 0000h | 2001 0000h | 2002 0000h | |
4h | I2C_REVNB_HI | 2000 0004h | 2001 0004h | 2002 0004h | |
10h | I2C_SYSC | 2000 0010h | 2001 0010h | 2002 0010h | |
20h | I2C_EOI | 2000 0020h | 2001 0020h | 2002 0020h | |
24h | I2C_IRQSTATUS_RAW | 2000 0024h | 2001 0024h | 2002 0024h | |
28h | I2C_IRQSTATUS | 2000 0028h | 2001 0028h | 2002 0028h | |
2Ch | I2C_IRQENABLE_SET | 2000 002Ch | 2001 002Ch | 2002 002Ch | |
30h | I2C_IRQENABLE_CLR | 2000 0030h | 2001 0030h | 2002 0030h | |
34h | I2C_WE | 2000 0034h | 2001 0034h | 2002 0034h | |
38h | I2C_DMARXENABLE_SET | 2000 0038h | 2001 0038h | 2002 0038h | |
3Ch | I2C_DMATXENABLE_SET | 2000 003Ch | 2001 003Ch | 2002 003Ch | |
40h | I2C_DMARXENABLE_CLR | 2000 0040h | 2001 0040h | 2002 0040h | |
44h | I2C_DMATXENABLE_CLR | 2000 0044h | 2001 0044h | 2002 0044h | |
48h | I2C_DMARXWAKE_EN | 2000 0048h | 2001 0048h | 2002 0048h | |
4Ch | I2C_DMATXWAKE_EN | 2000 004Ch | 2001 004Ch | 2002 004Ch | |
84h | I2C_IE | 2000 0084h | 2001 0084h | 2002 0084h | |
88h | I2C_STAT | 2000 0088h | 2001 0088h | 2002 0088h | |
90h | I2C_SYSS | 2000 0090h | 2001 0090h | 2002 0090h | |
94h | I2C_BUF | 2000 0094h | 2001 0094h | 2002 0094h | |
98h | I2C_CNT | 2000 0098h | 2001 0098h | 2002 0098h | |
9Ch | I2C_DATA | 2000 009Ch | 2001 009Ch | 2002 009Ch | |
A4h | I2C_CON | 2000 00A4h | 2001 00A4h | 2002 00A4h | |
A8h | I2C_OA | 2000 00A8h | 2001 00A8h | 2002 00A8h | |
ACh | I2C_SA | 2000 00ACh | 2001 00ACh | 2002 00ACh | |
B0h | I2C_PSC | 2000 00B0h | 2001 00B0h | 2002 00B0h | |
B4h | I2C_SCLL | 2000 00B4h | 2001 00B4h | 2002 00B4h | |
B8h | I2C_SCLH | 2000 00B8h | 2001 00B8h | 2002 00B8h | |
BCh | I2C_SYSTEST | 2000 00BCh | 2001 00BCh | 2002 00BCh | |
C0h | I2C_BUFSTAT | 2000 00C0h | 2001 00C0h | 2002 00C0h | |
C4h | I2C_OA1 | 2000 00C4h | 2001 00C4h | 2002 00C4h | |
C8h | I2C_OA2 | 2000 00C8h | 2001 00C8h | 2002 00C8h | |
CCh | I2C_OA3 | 2000 00CCh | 2001 00CCh | 2002 00CCh | |
D0h | I2C_ACTOA | 2000 00D0h | 2001 00D0h | 2002 00D0h | |
D4h | I2C_SBLOCK | 2000 00D4h | 2001 00D4h | 2002 00D4h |
Offset | Acronym | Register Name | I2C3_CFG Physical Address | MCU_I2C0_CFG Physical Address | MCU_I2C1_CFG Physical Address |
---|---|---|---|---|---|
0h | I2C_REVNB_LO | 2003 0000h | 0490 0000h | 0491 0000h | |
4h | I2C_REVNB_HI | 2003 0004h | 0490 0004h | 0491 0004h | |
10h | I2C_SYSC | 2003 0010h | 0490 0010h | 0491 0010h | |
20h | I2C_EOI | 2003 0020h | 0490 0020h | 0491 0020h | |
24h | I2C_IRQSTATUS_RAW | 2003 0024h | 0490 0024h | 0491 0024h | |
28h | I2C_IRQSTATUS | 2003 0028h | 0490 0028h | 0491 0028h | |
2Ch | I2C_IRQENABLE_SET | 2003 002Ch | 0490 002Ch | 0491 002Ch | |
30h | I2C_IRQENABLE_CLR | 2003 0030h | 0490 0030h | 0491 0030h | |
34h | I2C_WE | 2003 0034h | 0490 0034h | 0491 0034h | |
38h | I2C_DMARXENABLE_SET | 2003 0038h | 0490 0038h | 0491 0038h | |
3Ch | I2C_DMATXENABLE_SET | 2003 003Ch | 0490 003Ch | 0491 003Ch | |
40h | I2C_DMARXENABLE_CLR | 2003 0040h | 0490 0040h | 0491 0040h | |
44h | I2C_DMATXENABLE_CLR | 2003 0044h | 0490 0044h | 0491 0044h | |
48h | I2C_DMARXWAKE_EN | 2003 0048h | 0490 0048h | 0491 0048h | |
4Ch | I2C_DMATXWAKE_EN | 2003 004Ch | 0490 004Ch | 0491 004Ch | |
84h | I2C_IE | 2003 0084h | 0490 0084h | 0491 0084h | |
88h | I2C_STAT | 2003 0088h | 0490 0088h | 0491 0088h | |
90h | I2C_SYSS | 2003 0090h | 0490 0090h | 0491 0090h | |
94h | I2C_BUF | 2003 0094h | 0490 0094h | 0491 0094h | |
98h | I2C_CNT | 2003 0098h | 0490 0098h | 0491 0098h | |
9Ch | I2C_DATA | 2003 009Ch | 0490 009Ch | 0491 009Ch | |
A4h | I2C_CON | 2003 00A4h | 0490 00A4h | 0491 00A4h | |
A8h | I2C_OA | 2003 00A8h | 0490 00A8h | 0491 00A8h | |
ACh | I2C_SA | 2003 00ACh | 0490 00ACh | 0491 00ACh | |
B0h | I2C_PSC | 2003 00B0h | 0490 00B0h | 0491 00B0h | |
B4h | I2C_SCLL | 2003 00B4h | 0490 00B4h | 0491 00B4h | |
B8h | I2C_SCLH | 2003 00B8h | 0490 00B8h | 0491 00B8h | |
BCh | I2C_SYSTEST | 2003 00BCh | 0490 00BCh | 0491 00BCh | |
C0h | I2C_BUFSTAT | 2003 00C0h | 0490 00C0h | 0491 00C0h | |
C4h | I2C_OA1 | 2003 00C4h | 0490 00C4h | 0491 00C4h | |
C8h | I2C_OA2 | 2003 00C8h | 0490 00C8h | 0491 00C8h | |
CCh | I2C_OA3 | 2003 00CCh | 0490 00CCh | 0491 00CCh | |
D0h | I2C_ACTOA | 2003 00D0h | 0490 00D0h | 0491 00D0h | |
D4h | I2C_SBLOCK | 2003 00D4h | 0490 00D4h | 0491 00D4h |
I2C_REVNB_LO is shown in Figure 12-137 and described in Table 12-255.
Return to Summary Table.
Revision Number register (Low)
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0000h |
I2C1_CFG | 2001 0000h |
I2C2_CFG | 2002 0000h |
I2C3_CFG | 2003 0000h |
MCU_I2C0_CFG | 0490 0000h |
MCU_I2C1_CFG | 0491 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-1h | R-0h | R-0h | R-Ch | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-11 | RTL | R | 1h |
RTL version. |
10-8 | MAJOR | R | 0h |
Major Revision. This field changes when there is a major feature change. This field does not change due to bug fix, or minor feature change. |
7-6 | CUSTOM | R | 0h |
Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers. 0 if non-custom. |
5-0 | MINOR | R | Ch |
Minor Revision. This field changes when features are scaled up or down. This field does not change due to bug fix, or major feature change. |
I2C_REVNB_HI is shown in Figure 12-138 and described in Table 12-257.
Return to Summary Table.
Revision Number register (High)
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0004h |
I2C1_CFG | 2001 0004h |
I2C2_CFG | 2002 0004h |
I2C3_CFG | 2003 0004h |
MCU_I2C0_CFG | 0490 0004h |
MCU_I2C1_CFG | 0491 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SCHEME | RESERVED | FUNC | |||||
R-1h | R-1h | R-40h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FUNC | |||||||
R-40h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-14 | SCHEME | R | 1h |
Used to distinguish between old Scheme and current. Spare bit to encode future schemes. |
13-12 | RESERVED | R | 1h | Reads return 0x1. |
11-0 | FUNC | R | 40h | Function: Indicates a software compatible module family. |
I2C_SYSC is shown in Figure 12-139 and described in Table 12-259.
Return to Summary Table.
System Configuration register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0010h |
I2C1_CFG | 2001 0010h |
I2C2_CFG | 2002 0010h |
I2C3_CFG | 2003 0010h |
MCU_I2C0_CFG | 0490 0010h |
MCU_I2C1_CFG | 0491 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLKACTIVITY | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLEMODE | ENAWAKEUP | SRST | AUTOIDLE | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved. |
9-8 | CLKACTIVITY | R/W | 0h | Clock Activity selection bits. 0x0: Both clocks can be cut off. 0x1: Only OCP clock must be kept active; system clock can be cut off. 0x2: Only system clock must be kept active; OCP clock can be cut off. 0x3: Both clocks must be kept off. |
7-5 | RESERVED | R | 0h | Reads return 0. |
4-3 | IDLEMODE | R/W | 0h | Idle Mode selection bits. 0x0: Force Idle mode. 0x1: No Idle mode. 0x2: Smart Idle mode. 0x3: smartidle_wakeup. |
2 | ENAWAKEUP | R/W | 0h | Enable Wakeup control bit. 0: Wakeup mechanism is disabled. 1: Wakeup mechanism is enabled. |
1 | SRST | R/W | 0h | SoftReset bit. 0: Normal mode. 1: The module is reset. |
0 | AUTOIDLE | R/W | 1h | Autoidle bit. |
I2C_EOI is shown in Figure 12-140 and described in Table 12-261.
Return to Summary Table.
End Of Interrupt number specification
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0020h |
I2C1_CFG | 2001 0020h |
I2C2_CFG | 2002 0020h |
I2C3_CFG | 2003 0020h |
MCU_I2C0_CFG | 0490 0020h |
MCU_I2C1_CFG | 0491 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINE_NUMBER | ||||||
R-0h | W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved. |
0 | LINE_NUMBER | W | 0h | Software End Of Interrupt [EOI] control. Write number of interrupt output. |
I2C_IRQSTATUS_RAW is shown in Figure 12-141 and described in Table 12-263.
Return to Summary Table.
Per-event raw interrupt status vector
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0024h |
I2C1_CFG | 2001 0024h |
I2C2_CFG | 2002 0024h |
I2C3_CFG | 2003 0024h |
MCU_I2C0_CFG | 0490 0024h |
MCU_I2C1_CFG | 0491 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | BB | ROVR | XUDF | AAS | BF |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR | STC | GC | XRDY | RRDY | ARDY | NACK | AL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility. Read returns 0. |
14 | XDR | R/W | 0h | Transmit draining IRQ status. 0: Transmit draining inactive. 1: Transmit draining enabled. |
13 | RDR | R/W | 0h | Receive draining IRQ status. 0: Receive draining inactive. 1: Receive draining enabled. |
12 | BB | R | 0h | Bus busy status. Writing into this bit has no effect. Read 0: Bus is free. Read 1: Bus is occupied. |
11 | ROVR | R/W | 0h | Receive overrun status. Writing into this bit has no effect. Read 0: Normal operation. Read 1: Receiver overrun. |
10 | XUDF | R/W | 0h | Transmit underflow status. Writing into this bit has no effect. Read 0: Normal operation. Read 1: Transmit underflow. |
9 | AAS | R/W | 0h | Address recognized as target IRQ status. 0: No action. 1: Address recognized. |
8 | BF | R/W | 0h | Bus Free IRQ status. 0: No action. 1: BusFree. |
7 | AERR | R/W | 0h | Access Error IRQ status. 0: No action. 1: Access Error. |
6 | STC | R/W | 0h | Start Condition IRQ status. 0: No action. 1: Start Condition detected. |
5 | GC | R/W | 0h |
General call IRQ status. Set to '1' by core when General call address detected and interrupt signaled to MPUSS. Write '1' to clear. 0: No general call detected. 1: General call address detected. |
4 | XRDY | R/W | 0h | Transmit data ready IRQ status. Set to '1' by core when transmitter and when new data is requested. When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to clear. 0: Transmission ongoing. 1: Transmit data ready. |
3 | RRDY | R/W | 0h | Receive data ready IRQ status. Set to '1' by core when receiver mode, a new data is able to be read. When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to clear. 0: No data available. 1: Receive data available. |
2 | ARDY | R/W | 0h | Register access ready IRQ status. When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write '1' to clear. 0: Module busy. 1: Access ready. |
1 | NACK | R/W | 0h | No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write '1' to clear this bit. 0: Normal operation. 1: Not Acknowledge detected. |
0 | AL | R/W | 0h | Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in controller transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. 0: Normal operation. 1: Arbitration lost detected. |
I2C_IRQSTATUS is shown in Figure 12-142 and described in Table 12-265.
Return to Summary Table.
Per-event enabled interrupt status vector
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0028h |
I2C1_CFG | 2001 0028h |
I2C2_CFG | 2002 0028h |
I2C3_CFG | 2003 0028h |
MCU_I2C0_CFG | 0490 0028h |
MCU_I2C1_CFG | 0491 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | BB | ROVR | XUDF | AAS | BF |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR | STC | GC | XRDY | RRDY | ARDY | NACK | AL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility. Read returns 0. |
14 | XDR |
R/W |
0h | Transmit draining IRQ enabled status. Write '1' to clear. 0: Transmit draining inactive. 1: Transmit draining enabled. |
13 | RDR |
R/W |
0h | Receive draining IRQ enabled status. Write '1' to clear. 0: Receive draining inactive. 1: Receive draining enabled. |
12 | BB | R | 0h | Bus busy enabled status. Writing into this bit has no effect. Read 0: Bus is free. Read 1: Bus is occupied. |
11 | ROVR |
R/W |
0h | Receive overrun enabled status. Writing into this bit has no effect. Read 0: Normal operation. Read 1: Receiver overrun. |
10 | XUDF |
R/W |
0h | Transmit underflow enabled status. Writing into this bit has no effect. Read 0: Normal operation. Read 1: Transmit underflow. |
9 | AAS |
R/W |
0h | Address recognized as target IRQ enabled status. Write '1' to clear. 0: No action. 1: Address recognized. |
8 | BF |
R/W |
0h | Bus Free IRQ enabled status. Write '1' to clear. 0: No action. 1: Bus Free. |
7 | AERR |
R/W |
0h | Access Error IRQ enabled status. Write '1' to clear. 0: No action. 1: Access Error. |
6 | STC |
R/W |
0h | Start Condition IRQ enabled status. Write '1' to clear. 0: No action. 1: Start Condition detected. |
5 | GC |
R/W |
0h | General call IRQ enabled status. Set to '1' by core when General call address detected and interrupt signaled to MPUSS. Write '1' to clear. 0: No general call detected. 1: General call address detected. |
4 | XRDY |
R/W |
0h | Transmit data ready IRQ enabled status. Set to '1' by core when transmitter and when new data is requested. When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to clear. 0: Transmission ongoing. 1: Transmit data ready. |
3 | RRDY |
R/W |
0h | Receive data ready IRQ enabled status. Set to '1' by core when receiver mode, a new data is able to be read. When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to clear. 0: No data available. 1: Receive data available. |
2 | ARDY |
R/W |
0h | Register access ready IRQ enabled status. When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write '1' to clear. 0: Module busy. 1: Access ready. |
1 | NACK |
R/W |
0h | No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write '1' to clear this bit. 0: Normal operation. 1: Not Acknowledge detected. |
0 | AL |
R/W |
0h | Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in controller transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. Write '1' to clear. 0: Normal operation. 1: Arbitration lost detected. |
I2C_IRQENABLE_SET is shown in Figure 12-143 and described in Table 12-267.
Return to Summary Table.
Per-event interrupt enable bit vector.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 002Ch |
I2C1_CFG | 2001 002Ch |
I2C2_CFG | 2002 002Ch |
I2C3_CFG | 2003 002Ch |
MCU_I2C0_CFG | 0490 002Ch |
MCU_I2C1_CFG | 0491 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR_IE | RDR_IE | RESERVED | ROVR | XUDF | ASS_IE | BF_IE |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR_IE | STC_IE | GC_IE | XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE | AL_IE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility. Read returns 0. |
14 | XDR_IE | R/W | 0h | Transmit Draining interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]. 0: Transmit Draining interrupt disabled. 1: Transmit Draining interrupt enabled. |
13 | RDR_IE | R/W | 0h | Receive Draining interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]. Receive Draining interrupt disbaled. Receive Draining interrupt enabled. |
12 | RESERVED | R | 0h | Reserved. |
11 | ROVR | R/W | 0h | Receive overrun enable set. 0: Receive overrun interrupt disabled. 1: Receive overrun interrupt enabled. |
10 | XUDF | R/W | 0h | Transmit underflow enable set. 0: Transmit underflow interrupt disabled. 1: Transmit underflow interrupt enabled. |
9 | ASS_IE | R/W | 0h | Addressed as Target interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]. 0: Addressed as Target interrupt disabled. 1: Addressed as Target interrupt enabled. |
8 | BF_IE | R/W | 0h | Bus Free interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]. 0: Bus Free interrupt disabled. 1: Bus Free interrupt enabled. |
7 | AERR_IE | R/W | 0h | Access Error interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]. 0: Access Error interrupt disabled. 1: Access Error interrupt enabled. |
6 | STC_IE | R/W | 0h | Start Condition interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]. 0: Start Condition interrupt disabled. 1: Start Condition interrupt enabled. |
5 | GC_IE | R/W | 0h | General call Interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]. 0: General call interrupt disabled. 1: General call interrupt enabled. |
4 | XRDY_IE | R/W | 0h | Transmit data ready interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]. 0: Transmit data ready interrupt disabled. 1: Transmit data ready interrupt enabled. |
3 | RRDY_IE | R/W | 0h | Receive data ready interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]. 0: Receive data ready interrupt disabled. 1: Receive data ready interrupt enabled. |
2 | ARDY_IE | R/W | 0h | Register access ready interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]. 0: Register access ready interrupt disabled. 1: Register access ready interrupt enabled. |
1 | NACK_IE | R/W | 0h | No acknowledgement interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]. 0: Not acknowledge interrupt disabled. 1: Not acknowledge interrupt enabled. |
0 | AL_IE | R/W | 0h | Arbitration lost interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]. 0: Arbitration lost interrupt disabled. 1: Arbitration lost interrupt enabled. |
I2C_IRQENABLE_CLR is shown in Figure 12-144 and described in Table 12-269.
Return to Summary Table.
Per-event interrupt clear bit vector.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0030h |
I2C1_CFG | 2001 0030h |
I2C2_CFG | 2002 0030h |
I2C3_CFG | 2003 0030h |
MCU_I2C0_CFG | 0490 0030h |
MCU_I2C1_CFG | 0491 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR_IE | RDR_IE | RESERVED | ROVR | XUDF | ASS_IE | BF_IE |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR_IE | STC_IE | GC_IE | XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE | AL_IE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility. Read returns 0. |
14 | XDR_IE | R/W | 0h | Transmit Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]. 0: Transmit Draining interrupt disabled. 1: Transmit Draining interrupt enabled. |
13 | RDR_IE | R/W | 0h | Receive Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]. 0: Receive Draining interrupt disabled. 1: Receive Draining interrupt enabled. |
12 | RESERVED | R | 0h | Reserved. |
11 | ROVR | R/W | 0h | Receive overrun enable clear. 0: Receive overrun interrupt disabled. 1: Receive overrup interrupt enabled. |
10 | XUDF | R/W | 0h | Transmit underflow enable clear. 0: Transmit underflow interrupt disabled. 1: Transmit underflow interrupt enabled. |
9 | ASS_IE | R/W | 0h | Addressed as Target interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]. 0: Addressed as Target interrupt disabled. 1: Addressed as Target interrupt enabled. |
8 | BF_IE | R/W | 0h | Bus Free interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]. 0: Bus Free interrupt disabled. 1: Bus Free interrupt enabled. |
7 | AERR_IE | R/W | 0h | Access Error interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]. 0: Access Error interrupt disabled. 1: Access Error interrupt enabled. |
6 | STC_IE | R/W | 0h | Start Condition interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]. 0: Start Condition interrupt disabled. 1: Start Condition interrupt enabled. |
5 | GC_IE | R/W | 0h | General call Interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]. 0: General call interrupt disabled. 1: General call interrupt enabled. |
4 | XRDY_IE | R/W | 0h | Transmit data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]. 0: Transmit data ready interrupt disabled. 1: Transmit data ready interrupt enabled. |
3 | RRDY_IE | R/W | 0h | Receive data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]. 0: Receive data ready interrupt disabled. 1: Receive data ready interrupt enabled. |
2 | ARDY_IE | R/W | 0h | Register access ready interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]. 0: Register access ready interrupt disabled. 1: Register access ready interrupt enabled. |
1 | NACK_IE | R/W | 0h | No acknowledgement interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]. 0: Not Acknowledge interrupt disabled. 1: Not Acknowledge interrupt enabled. |
0 | AL_IE | R/W | 0h | Arbitration lost interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]. 0: Arbitration lost interrupt disabled. 1: Arbitration lost interrupt enabled. |
I2C_WE is shown in Figure 12-145 and described in Table 12-271.
Return to Summary Table.
I2C wakeup enable vector (legacy).
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0034h |
I2C1_CFG | 2001 0034h |
I2C2_CFG | 2002 0034h |
I2C3_CFG | 2003 0034h |
MCU_I2C0_CFG | 0490 0034h |
MCU_I2C1_CFG | 0491 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | RESERVED | ROVR | XUDF | AAS | BF |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STC | GC | RESERVED | DRDY | ARDY | NACK | AL |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R | 0h | Reserved. |
14 | XDR | R/W | 0h | Transmit Draining wakeup set. 0: Transmit draining wakeup disabled. 1: Transmit draining wakeup enabled. |
13 | RDR | R/W | 0h | Receive Draining wakeup set. 0: Receive draining wakeup disabled. 1: Receive draining wakeup enabled. |
12 | RESERVED | R | 0h | Reserved. |
11 | ROVR | R/W | 0h | Receive overrun wakeup set. 0: Receive overrun wakeup disabled. 1: Receive overrun wakeup enabled. |
10 | XUDF | R/W | 0h | Transmit underflow wakeup set. 0: Transmit underflow wakeup disabled. 1: Transmit underflow wakeup enabled. |
9 | AAS | R/W | 0h | Address as target IRQ wakeup set. 0: Addressed as target wakeup disabled. 1: Addressed as target wakeup enabled. |
8 | BF | R/W | 0h | Bus Free IRQ wakeup set. 0: Bus Free wakeup disabled. 1: Bus Free wakeup enabled. |
7 | RESERVED | R | 0h | Reserved. |
6 | STC | R/W | 0h | Start Condition IRQ wakeup set. 0: Start condition wakeup disbaled. 1: Start condition wakeup enabled. |
5 | GC | R/W | 0h | General call IRQ wakeup set. 0: General call wakeup disabled. 1: General call wakeup enabled. |
4 | RESERVED | R | 0h | Reserved. |
3 | DRDY | R/W | 0h | Receive/Transmit data ready IRQ wakeup set. 0: Transmit/receive data ready wakeup disabled. 1: Transmit/receive data ready wakeup enabled. |
2 | ARDY | R/W | 0h | Register access ready IRQ wakeup set. 0: Register access ready wakeup disabled. 1: Register access ready wakeup enabled. |
1 | NACK | R/W | 0h | No acknowledgment IRQ wakeup set. 0: Not Acknowledge wakeup disabled. 1: Not Acknowledge wakeup enabled. |
0 | AL | R/W | 0h | Arbitration lost IRQ wakeup set. 0: Arbitration lost wakeup disabled. 1: Arbitration lost wakeup enabled. |
I2C_DMARXENABLE_SET is shown in Figure 12-146 and described in Table 12-273.
Return to Summary Table.
Per-event DMA RX enable set.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0038h |
I2C1_CFG | 2001 0038h |
I2C2_CFG | 2002 0038h |
I2C3_CFG | 2003 0038h |
MCU_I2C0_CFG | 0490 0038h |
MCU_I2C1_CFG | 0491 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMARX_ENABLE_SET | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved. |
0 | DMARX_ENABLE_SET | R/W | 0h | Receive DMA channel enable set. |
I2C_DMATXENABLE_SET is shown in Figure 12-147 and described in Table 12-275.
Return to Summary Table.
Per-event DMA TX enable set.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 003Ch |
I2C1_CFG | 2001 003Ch |
I2C2_CFG | 2002 003Ch |
I2C3_CFG | 2003 003Ch |
MCU_I2C0_CFG | 0490 003Ch |
MCU_I2C1_CFG | 0491 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMATX_ENABLE_SET | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved. |
0 | DMATX_ENABLE_SET | R/W | 0h | Transmit DMA channel enable set. |
I2C_DMARXENABLE_CLR is shown in Figure 12-148 and described in Table 12-277.
Return to Summary Table.
Per-event DMA RX enable clear.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0040h |
I2C1_CFG | 2001 0040h |
I2C2_CFG | 2002 0040h |
I2C3_CFG | 2003 0040h |
MCU_I2C0_CFG | 0490 0040h |
MCU_I2C1_CFG | 0491 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMARX_ENABLE_CLEAR | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved. |
0 | DMARX_ENABLE_CLEAR | R/W | 0h | Receive DMA channel enable clear. |
I2C_DMATXENABLE_CLR is shown in Figure 12-149 and described in Table 12-279.
Return to Summary Table.
Per-event DMA TX enable clear.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0044h |
I2C1_CFG | 2001 0044h |
I2C2_CFG | 2002 0044h |
I2C3_CFG | 2003 0044h |
MCU_I2C0_CFG | 0490 0044h |
MCU_I2C1_CFG | 0491 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMATX_ENABLE_CLEAR | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved. |
0 | DMATX_ENABLE_CLEAR | R/W | 0h | Transmit DMA channel enable clear. |
I2C_DMARXWAKE_EN is shown in Figure 12-150 and described in Table 12-281.
Return to Summary Table.
Per-event DMA RX wakeup enable.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0048h |
I2C1_CFG | 2001 0048h |
I2C2_CFG | 2002 0048h |
I2C3_CFG | 2003 0048h |
MCU_I2C0_CFG | 0490 0048h |
MCU_I2C1_CFG | 0491 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | RESERVED | ROVR | XUDF | AAS | BF |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STC | GC | RESERVED | DRDY | ARDY | NACK | AL |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R | 0h | Reserved. |
14 | XDR | R/W | 0h | Transmit Draining wakeup set. 0: Transmit draining wakeup disabled. 1: Transmit draining wakeup enabled. |
13 | RDR | R/W | 0h | Receive Draining wakeup set. 0: Receive draining wakeup disabled. 1: Receive draining wakeup enabled. |
12 | RESERVED | R | 0h | Reserved. |
11 | ROVR | R/W | 0h | Receive overrun wakeup set. 0: Receive overrun wakeup disabled. 1: Receive overrun wakeup enabled. |
10 | XUDF | R/W | 0h | Transmit underflow wakeup set. 0: Transmit underflow wakeup disabled. 1: Transmit underflow wakeup enabled. |
9 | AAS | R/W | 0h | Address as target IRQ wakeup set. 0: Addressed as target wakeup disabled. 1: Addressed as target wakeup enabled. |
8 | BF | R/W | 0h | Bus Free IRQ wakeup set. 0: Bus Free wakeup disabled. 1: Bus Free wakeup enabled. |
7 | RESERVED | R | 0h | Reserved. |
6 | STC | R/W | 0h | Start Condition IRQ wakeup set. 0: Start condition wakeup disabled. 1: Start condition wakeup enabled. |
5 | GC | R/W | 0h | General call IRQ wakeup set. 0: General call wakeup disabled. 1: General call wakeup enabled. |
4 | RESERVED | R | 0h | Reserved. |
3 | DRDY | R/W | 0h | Receive/Transmit data ready IRQ wakeup set. 0: Transmit/Receive data ready wakeup disabled. 1: Transmit/Receive data ready wakeup enabled |
2 | ARDY | R/W | 0h | Register access ready IRQ wakeup set. 0: Register access ready wakeup disabled. 1: Register access ready wakeup enabled. |
1 | NACK | R/W | 0h | No acknowledgment IRQ wakeup set. 0: Not Acknowledge wakeup disbaled. 1: Not Acknowledge wakeup enabled. |
0 | AL | R/W | 0h | Arbitration lost IRQ wakeup set. 0: Arbitration lost wakeup disabled. 1: Arbitration lost wakeup enabled. |
I2C_DMATXWAKE_EN is shown in Figure 12-151 and described in Table 12-283.
Return to Summary Table.
Per-event DMA TX wakeup enable.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 004Ch |
I2C1_CFG | 2001 004Ch |
I2C2_CFG | 2002 004Ch |
I2C3_CFG | 2003 004Ch |
MCU_I2C0_CFG | 0490 004Ch |
MCU_I2C1_CFG | 0491 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | RESERVED | ROVR | XUDF | AAS | BF |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STC | GC | RESERVED | DRDY | ARDY | NACK | AL |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R | 0h | Reserved. |
14 | XDR | R/W | 0h | Transmit Draining wakeup set. 0: Transmit draining wakeup disabled. 1: Transmit draining wakeup enabled. |
13 | RDR | R/W | 0h | Receive Draining wakeup set. 0: Receive draining wakeup disabled. 1: Receive draining wakeup enabled. |
12 | RESERVED | R | 0h | Reserved. |
11 | ROVR | R/W | 0h | Receive overrun wakeup set. 0: Receive overrun wakeup disabled. 1: Receive overrun wakeup enabled. |
10 | XUDF | R/W | 0h | Transmit underflow wakeup set. 0: Transmit underflow wakeup disabled. 1: Transmit underflow wakeup enabled. |
9 | AAS | R/W | 0h | Address as target IRQ wakeup set. 0: Addressed as target wakeup disabled. 1: Addressed as target wakeup enabled. |
8 | BF | R/W | 0h | Bus Free IRQ wakeup set. 0: Bus Free wakeup disabled. 1: Bus Free wakeup enabled. |
7 | RESERVED | R | 0h | Reserved. |
6 | STC | R/W | 0h | Start Condition IRQ wakeup set. 0: Start condition wakeup disabled. 1: Start condition wakeup enabled. |
5 | GC | R/W | 0h | General call IRQ wakeup set. 0: General call wakeup disabled. 1: General call wakeup enabled. |
4 | RESERVED | R | 0h | Reserved. |
3 | DRDY | R/W | 0h | Receive/Transmit data ready IRQ wakeup set. 0: Transmit/receive data ready wakeup. 1: Transmit/receive data ready wakeup. |
2 | ARDY | R/W | 0h | Register access ready IRQ wakeup set. 0: Register access ready wakeup disabled. 1: Register access ready wakeup enabled. |
1 | NACK | R/W | 0h | No acknowledgment IRQ wakeup set. 0: Not Acknowledge wakeup disabled. 1: Not Acknowledge wakeup enabled. |
0 | AL | R/W | 0h | Arbitration lost IRQ wakeup set. 0: Arbitration lost wakeup disabled. 1: Arbitration lost wakeup enabled. |
I2C_IE is shown in Figure 12-152 and described in Table 12-285.
Return to Summary Table.
I2C interrupt enable vector (legacy).
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0084h |
I2C1_CFG | 2001 0084h |
I2C2_CFG | 2002 0084h |
I2C3_CFG | 2003 0084h |
MCU_I2C0_CFG | 0490 0084h |
MCU_I2C1_CFG | 0491 0084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR_IE | RDR_IE | RESERVED | ROVR | XUDF | ASS_IE | BF_IE |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR_IE | STC_IE | GC_IE | XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE | AL_IE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility. Read returns 0. |
14 | XDR_IE | R/W | 0h | Transmit Draining interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]. |
13 | RDR_IE | R/W | 0h | Receive Draining interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]. |
12 | RESERVED | R | 0h | Reserved. |
11 | ROVR | R/W | 0h | Receive overrun enable set. |
10 | XUDF | R/W | 0h | Transmit underflow enable set. |
9 | ASS_IE | R/W | 0h | Addressed as Target interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]. |
8 | BF_IE | R/W | 0h |
Bus Free interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]. |
7 | AERR_IE | R/W | 0h | Access Error interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]. |
6 | STC_IE | R/W | 0h | Start Condition interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]. |
5 | GC_IE | R/W | 0h | General call Interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]. |
4 | XRDY_IE | R/W | 0h | Transmit data ready interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]. |
3 | RRDY_IE | R/W | 0h | Receive data ready interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]. |
2 | ARDY_IE | R/W | 0h | Register access ready interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]. |
1 | NACK_IE | R/W | 0h | No acknowledgement interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]. |
0 | AL_IE | R/W | 0h | Arbitration lost interrupt enable. Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]. |
I2C_STAT is shown in Figure 12-153 and described in Table 12-287.
Return to Summary Table.
I2C interrupt status vector (legacy).
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0088h |
I2C1_CFG | 2001 0088h |
I2C2_CFG | 2002 0088h |
I2C3_CFG | 2003 0088h |
MCU_I2C0_CFG | 0490 0088h |
MCU_I2C1_CFG | 0491 0088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | BB | ROVR | XUDF | AAS | BF |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR | STC | GC | XRDY | RRDY | ARDY | NACK | AL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility. Read returns 0. |
14 | XDR | R/W | 0h | Transmit draining IRQ status. |
13 | RDR | R/W | 0h | Receive draining IRQ status. |
12 | BB | R | 0h | Bus busy status. Writing into this bit has no effect. |
11 | ROVR | R/W | 0h | Receive overrun status. Writing into this bit has no effect. |
10 | XUDF | R/W | 0h | Transmit underflow status. Writing into this bit has no effect. |
9 | AAS | R/W | 0h | Address recognized as target IRQ status. |
8 | BF | R/W | 0h | Bus Free IRQ status. |
7 | AERR | R/W | 0h | Access Error IRQ status. |
6 | STC | R/W | 0h | Start Condition IRQ status. |
5 | GC | R/W | 0h | General call IRQ status. Set to '1' by core when General call address detected and interrupt signaled to MPUSS. Write '1' to clear. |
4 | XRDY | R/W | 0h | Transmit data ready IRQ status. Set to '1' by core when transmitter and when new data is requested. When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to clear. |
3 | RRDY | R/W | 0h | Receive data ready IRQ status. Set to '1' by core when receiver mode, a new data is able to be read. When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to clear. |
2 | ARDY | R/W | 0h | Register access ready IRQ status. When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write '1' to clear. |
1 | NACK | R/W | 0h | No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write '1' to clear this bit. |
0 | AL | R/W | 0h | Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in controller transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. |
I2C_SYSS is shown in Figure 12-154 and described in Table 12-289.
Return to Summary Table.
System Status register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0090h |
I2C1_CFG | 2001 0090h |
I2C2_CFG | 2002 0090h |
I2C3_CFG | 2003 0090h |
MCU_I2C0_CFG | 0490 0090h |
MCU_I2C1_CFG | 0491 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDONE | ||||||
R-0h | R-1h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-1 | RESERVED | R | 0h | Reserved. |
0 | RDONE | R | 1h | Reset done bit. Read 0: Internal module reset in on-going. Read 1: Reset completed. |
I2C_BUF is shown in Figure 12-155 and described in Table 12-291.
Return to Summary Table.
Buffer Configuration register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0094h |
I2C1_CFG | 2001 0094h |
I2C2_CFG | 2002 0094h |
I2C3_CFG | 2003 0094h |
MCU_I2C0_CFG | 0490 0094h |
MCU_I2C1_CFG | 0491 0094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RDMA_EN | RXFIFO_CLR | RXTRSH | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XDMA_EN | TXFIFO_CLR | TXTRSH | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RDMA_EN | R/W | 0h | Receive DMA channel enable. 0: Receive DMA channel disabled. 1: Receive DMA channel enabled. |
14 | RXFIFO_CLR | R/W | 0h | Receive FIFO clear. 0: Normal mode. 1: Rx FIFO is reset. |
13-8 | RXTRSH | R/W | 0h | Threshold value for FIFO buffer in RX mode. |
7 | XDMA_EN | R/W | 0h | Transmit DMA channel enable. 0: Transmit DMA channel disabled. 1: Transmit DMA channel enabled. |
6 | TXFIFO_CLR | R/W | 0h | Transmit FIFO clear. 0: Normal mode. 1: Tx FIFO is reset. |
5-0 | TXTRSH | R/W | 0h | Threshold value for FIFO buffer in TX mode. |
I2C_CNT is shown in Figure 12-156 and described in Table 12-293.
Return to Summary Table.
Data counter register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 0098h |
I2C1_CFG | 2001 0098h |
I2C2_CFG | 2002 0098h |
I2C3_CFG | 2003 0098h |
MCU_I2C0_CFG | 0490 0098h |
MCU_I2C1_CFG | 0491 0098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCOUNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | DCOUNT | R/W | 0h | Data count. |
I2C_DATA is shown in Figure 12-157 and described in Table 12-295.
Return to Summary Table.
Data access register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 009Ch |
I2C1_CFG | 2001 009Ch |
I2C2_CFG | 2002 009Ch |
I2C3_CFG | 2003 009Ch |
MCU_I2C0_CFG | 0490 009Ch |
MCU_I2C1_CFG | 0491 009Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | DATA | |||||||||||||||||||||||||||||
R/W-X | R-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | RESERVED | R | 0h | Reserved. |
7-0 | DATA | R/W | 0h | Transmit/Receive data FIFO endpoint. |
I2C_CON is shown in Figure 12-158 and described in Table 12-297.
Return to Summary Table.
I2C configuration register.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00A4h |
I2C1_CFG | 2001 00A4h |
I2C2_CFG | 2002 00A4h |
I2C3_CFG | 2003 00A4h |
MCU_I2C0_CFG | 0490 00A4h |
MCU_I2C1_CFG | 0491 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
I2C_EN | RESERVED | OPMODE | STB | MST | TRX | XSA | |
R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XOA0 | XOA1 | XOA2 | XOA3 | RESERVED | STP | STT | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | I2C_EN | R/W | 0h | I2C module enable. 0: controller in reset. FIFO are cleared and status bits are set to their default value. 1: Module enabled. |
14 | RESERVED | R | 0h | Reserved |
13-12 | OPMODE | R/W | 0h | Operation mode selection. 0x0: I2C Fast/Standard mode. 0x1: I2C High Speed mode. 0x2: SCCB mode. 0x3: Reserved. |
11 | STB | R/W | 0h | Start byte mode [controller mode only]. 0: Normal mode. 1: Start byte mode. |
10 | MST | R/W | 0h | Controller/target mode. 0: Target mode. 1: Controller mode. |
9 | TRX | R/W | 0h | Transmitter/Receiver mode [controller mode only]. 0: Received mode. 1: Transmitter mode. |
8 | XSA | R/W | 0h | Expand Target address. 0: 7-bit address mode. 1: 10-bit address mode. |
7 | XOA0 | R/W | 0h | Expand Own address 0. 0: 7-bit address mode. 1: 10-bit address mode. |
6 | XOA1 | R/W | 0h | Expand Own address 1. 0: 7-bit address mode. 1: 10-bit address mode. |
5 | XOA2 | R/W | 0h | Expand Own address 2. 0: 7-bit address mode. 1: 10-bit address mode. |
4 | XOA3 | R/W | 0h | Expand Own address 3. 0: 7-bit address mode. 1: 10-bit address mode. |
3-2 | RESERVED | R | 0h | Reserved. |
1 | STP | R/W | 0h | Stop condition [controller mode only]. 0: No action or stop condition detected. 1: Stop condition queried. |
0 | STT | R/W | 0h | Start condition [controller mode only]. 0: No action or start condition detected. 1: Start condition queried. |
I2C_OA is shown in Figure 12-159 and described in Table 12-299.
Return to Summary Table.
Own address register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00A8h |
I2C1_CFG | 2001 00A8h |
I2C2_CFG | 2002 00A8h |
I2C3_CFG | 2003 00A8h |
MCU_I2C0_CFG | 0490 00A8h |
MCU_I2C1_CFG | 0491 00A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCODE | RESERVED | OA | |||||||||||||
R/W-0h | R-0h | R/W-0h | |||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-13 | MCODE | R/W | 0h | Controller Code. |
12-10 | RESERVED | R | 0h | Reserved. |
9-0 | OA | R/W | 0h | Own address. |
I2C_SA is shown in Figure 12-160 and described in Table 12-301.
Return to Summary Table.
Target address register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00ACh |
I2C1_CFG | 2001 00ACh |
I2C2_CFG | 2002 00ACh |
I2C3_CFG | 2003 00ACh |
MCU_I2C0_CFG | 0490 00ACh |
MCU_I2C1_CFG | 0491 00ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SA | ||||||||||||||
R-0h | R/W-3FFh | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved. |
9-0 | SA | R/W | 3FFh | Target address. |
I2C_PSC is shown in Figure 12-161 and described in Table 12-303.
Return to Summary Table.
I2C Clock Prescaler Register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00B0h |
I2C1_CFG | 2001 00B0h |
I2C2_CFG | 2002 00B0h |
I2C3_CFG | 2003 00B0h |
MCU_I2C0_CFG | 0490 00B0h |
MCU_I2C1_CFG | 0491 00B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | PSC | |||||||||||||||||||||||||||||
R/W-X | R-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | RESERVED | R | 0h | Reserved. |
7-0 | PSC | R/W | 0h | Fast/Standard mode prescale sampling clock divider value. |
I2C_SCLL is shown in Figure 12-162 and described in Table 12-305.
Return to Summary Table.
I2C SCL Low Time Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00B4h |
I2C1_CFG | 2001 00B4h |
I2C2_CFG | 2002 00B4h |
I2C3_CFG | 2003 00B4h |
MCU_I2C0_CFG | 0490 00B4h |
MCU_I2C1_CFG | 0491 00B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSSCLL | SCLL | |||||||||||||||||||||||||||||
R/W-X | R/W-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | HSSCLL | R/W | 0h | High Speed mode SCL low time. |
7-0 | SCLL | R/W | 0h | Fast/Standard mode SCL low time. |
I2C_SCLH is shown in Figure 12-163 and described in Table 12-307.
Return to Summary Table.
I2C SCL High Time Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00B8h |
I2C1_CFG | 2001 00B8h |
I2C2_CFG | 2002 00B8h |
I2C3_CFG | 2003 00B8h |
MCU_I2C0_CFG | 0490 00B8h |
MCU_I2C1_CFG | 0491 00B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSSCLH | SCLH | |||||||||||||||||||||||||||||
R/W-X | R/W-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | HSSCLH | R/W | 0h | High Speed mode SCL high time. |
7-0 | SCLH | R/W | 0h | Fast/Standard mode SCL high time. |
I2C_SYSTEST is shown in Figure 12-164 and described in Table 12-309.
Return to Summary Table.
I2C System Test Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00BCh |
I2C1_CFG | 2001 00BCh |
I2C2_CFG | 2002 00BCh |
I2C3_CFG | 2003 00BCh |
MCU_I2C0_CFG | 0490 00BCh |
MCU_I2C1_CFG | 0491 00BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ST_EN | FREE | TMODE | SSB | RESERVED | SCL_I_FUNC | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R-1h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCL_O_FUNC | SDA_I_FUNC | SDA_O_FUNC | SCCB_E_O | SCL_I | SCL_O | SDA_I | SDA_O |
R-1h | R-1h | R-1h | R/W-0h | R-0h | R/W-0h | R-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | ST_EN | R/W | 0h |
System test enable. 0: Normal mode. All other bits in register are read only. 1: System test enabled. Permit other sytsem test register bits to be set. |
14 | FREE | R/W | 0h | Free running mode [on breakpoint]. 0: Stop mode [on breakpoint condition]. If Controller mode, it stops after completion of the on-going bit transfer. In target mode, it stops during the phase transfer when 1 byte is completely transmitted/received. 1: Free running mode |
13-12 | TMODE | R/W | 0h | Test mode select. 0x0: Functional mode [default]. 0x1: Reserved. 0x2: Test of SCL counters [SCLL, SCLH, PSC]. SCL provides a permanent clock with controller mode. 0x3: Loop back mode select + SDA/SCL IO mode select. |
11 | SSB | R/W | 0h | Set status bits. 0: No action. 1: Set all interrupt status bits to 1. |
10-9 | RESERVED | R | 0h | Reserved |
8 | SCL_I_FUNC | R | 1h | SCL line input value [functional mode]. Read 0: Read 0 from SCL line. Read 1: Read 1 from SCL line. |
7 | SCL_O_FUNC | R | 1h | SCL line output value [functional mode]. Read 0: Driven 0 on SCL line. Read 1: Driven 1 on SCL line. |
6 | SDA_I_FUNC | R | 1h | SDA line input value [functional mode]. Read 0: Read 0 from SDA line. Read 1: Read 1 from SDA line. |
5 | SDA_O_FUNC | R | 1h | SDA line output value [functional mode]. Read 0: Driven 0 to SDA line. Read 1: Driven 1 to SDA line. |
4 | SCCB_E_O | R/W | 0h | SCCB_E line sense output value. 0: Write 0 to SCCBE line. 1: Write 1 to SCCBE line. |
3 | SCL_I | R | 0h | SCL line sense input value. Read 0: Read 0 from SCL line. Read 1: Read 1 from SCL line. |
2 | SCL_O | R/W | 0h | SCL line drive output value. 0: Write 0 to SCL line. 1: Write 1 to SCL line. |
1 | SDA_I | R | 0h | SDA line sense input value. Read 0: Read 0 from SDA line. Read 1: Read 1 from SDA line. |
0 | SDA_O | R/W | 0h | SDA line drive output value. 0: Write 0 to SDA line. 1: Write 1 to SDA line. |
I2C_BUFSTAT is shown in Figure 12-165 and described in Table 12-311.
Return to Summary Table.
I2C Buffer Status Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00C0h |
I2C1_CFG | 2001 00C0h |
I2C2_CFG | 2002 00C0h |
I2C3_CFG | 2003 00C0h |
MCU_I2C0_CFG | 0490 00C0h |
MCU_I2C1_CFG | 0491 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FIFODEPTH | RXSTAT | ||||||
R-2h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXSTAT | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-14 | FIFODEPTH | R | 2h | Internal FIFO buffers depth. Read 0x0: 8-bytes FIFO. Read 0x1: 16-bytes FIFO. Read 0x2: 32-bytes FIFO. Read 0x3: 64-bytes FIFO. |
13-8 | RXSTAT | R | 0h | RX Buffer Status. |
7-6 | RESERVED | R | 0h | Reserved. |
5-0 | TXSTAT | R | 0h | TX Buffer Status. |
I2C_OA1 is shown in Figure 12-166 and described in Table 12-313.
Return to Summary Table.
I2C Own Address 1 Register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00C4h |
I2C1_CFG | 2001 00C4h |
I2C2_CFG | 2002 00C4h |
I2C3_CFG | 2003 00C4h |
MCU_I2C0_CFG | 0490 00C4h |
MCU_I2C1_CFG | 0491 00C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA1 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved. |
9-0 | OA1 | R/W | 0h | Own address 1. |
I2C_OA2 is shown in Figure 12-167 and described in Table 12-315.
Return to Summary Table.
I2C Own Address 2 Register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00C8h |
I2C1_CFG | 2001 00C8h |
I2C2_CFG | 2002 00C8h |
I2C3_CFG | 2003 00C8h |
MCU_I2C0_CFG | 0490 00C8h |
MCU_I2C1_CFG | 0491 00C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA2 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved. |
9-0 | OA2 | R/W | 0h | Own address 2. |
I2C_OA3 is shown in Figure 12-168 and described in Table 12-317.
Return to Summary Table.
I2C Own Address 3 Register
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00CCh |
I2C1_CFG | 2001 00CCh |
I2C2_CFG | 2002 00CCh |
I2C3_CFG | 2003 00CCh |
MCU_I2C0_CFG | 0490 00CCh |
MCU_I2C1_CFG | 0491 00CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA3 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved. |
9-0 | OA3 | R/W | 0h | Own address 3. |
I2C_ACTOA is shown in Figure 12-169 and described in Table 12-319.
Return to Summary Table.
I2C Active Own Address Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00D0h |
I2C1_CFG | 2001 00D0h |
I2C2_CFG | 2002 00D0h |
I2C3_CFG | 2003 00D0h |
MCU_I2C0_CFG | 0490 00D0h |
MCU_I2C1_CFG | 0491 00D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA3_ACT | OA2_ACT | OA1_ACT | OA0_ACT | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-4 | RESERVED | R | 0h | Reserved. |
3 | OA3_ACT | R | 0h | Own Address 3 active. Read 0: Own Address inactive. Read 1: Own Address active. |
2 | OA2_ACT | R | 0h | Own Address 2 active. Read 0: Own Address inactive. Read 1: Own Address active. |
1 | OA1_ACT | R | 0h | Own Address 1 active. Read 0: Own Address inactive. Read 1: Own Address active. |
0 | OA0_ACT | R | 0h | Own Address 0 active. Read 0: Own Address inactive. Read 1: Own Address active. |
I2C_SBLOCK is shown in Figure 12-170 and described in Table 12-321.
Return to Summary Table.
I2C Clock Blocking Enable Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 2000 00D4h |
I2C1_CFG | 2001 00D4h |
I2C2_CFG | 2002 00D4h |
I2C3_CFG | 2003 00D4h |
MCU_I2C0_CFG | 0490 00D4h |
MCU_I2C1_CFG | 0491 00D4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA3_EN | OA2_EN | OA1_EN | OA0_EN | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-4 | RESERVED | R | 0h | Reserved. |
3 | OA3_EN | R/W | 0h | Enable I2C Clock Blocking for Own Address 3. 0: I2C Clock Released. 1: I2C Clock Blocked. |
2 | OA2_EN | R/W | 0h | Enable I2C Clock Blocking for Own Address 2. 0: I2C Clock Released. 1: I2C Clock Blocked. |
1 | OA1_EN | R/W | 0h | Enable I2C Clock Blocking for Own Address 1. 0: I2C Clock Released. 1: I2C Clock Blocked. |
0 | OA0_EN | R/W | 0h | Enable I2C Clock Blocking for Own Address 0. 0: I2C Clock Released. 1: I2C Clock Blocked. |