ZHCSJI6 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
Address: 0x1B
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Reserved | BUCK1_PG
_INT |
BUCK1_SC
_INT |
BUCK1_ILIM
_INT |
Reserved | BUCK0_PG
_INT |
BUCK0_SC
_INT |
BUCK0_ILIM
_INT |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7 | Reserved | R/W | 0 | |
6 | BUCK1_PG_INT | R/W | 0 | Latched status bit indicating that Buck1 Power-Good event has been detected.
Write 1 to clear. |
5 | BUCK1_SC_INT | R/W | 0 | Latched status bit indicating that the Buck1 output voltage has been over 1 ms below short-circuit threshold level.
Write 1 to clear. |
4 | BUCK1_ILIM_INT | R/W | 0 | Latched status bit indicating that the Buck1 output current limit has been active.
Write 1 to clear. |
3 | Reserved | R/W | 0 | |
2 | BUCK0_PG_INT | R/W | 0 | Latched status bit indicating that Buck0 Power-Good event has been detected.
Write 1 to clear. |
1 | BUCK0_SC_INT | R/W | 0 | Latched status bit indicating that the Buck0 output voltage has been over 1 ms below short-circuit threshold level.
Write 1 to clear. |
0 | BUCK0_ILIM_INT | R/W | 0 | Latched status bit indicating that the Buck0 output current limit has been active.
Write 1 to clear. |