ZHCSJI6 March   2019 TPS65653-Q1

PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.  

  1. 1 特性
    1.     简化原理图
  2. 2 应用
  3. 3 说明
    1.     直流/直流效率与输出电流
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
        2. 7.3.4.2 Changing Output Voltage
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
          1. 7.3.7.1.1 PGOOD Pin Gated mode
          2. 7.3.7.1.2 PGOOD Pin Continuous Mode
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 Operation of the GPO Signals
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
        2. 7.6.1.2  OTP_REV
        3. 7.6.1.3  BUCK0_CTRL_1
        4. 7.6.1.4  BUCK0_CTRL_2
        5. 7.6.1.5  BUCK1_CTRL_1
        6. 7.6.1.6  BUCK1_CTRL_2
        7. 7.6.1.7  BUCK0_VOUT
        8. 7.6.1.8  BUCK1_VOUT
        9. 7.6.1.9  BUCK0_DELAY
        10. 7.6.1.10 BUCK1_DELAY
        11. 7.6.1.11 GPO_DELAY
        12. 7.6.1.12 GPO2_DELAY
        13. 7.6.1.13 GPO_CTRL
        14. 7.6.1.14 CONFIG
        15. 7.6.1.15 PLL_CTRL
        16. 7.6.1.16 PGOOD_CTRL_1
        17. 7.6.1.17 PGOOD_CTRL_2
        18. 7.6.1.18 PG_FAULT
        19. 7.6.1.19 RESET
        20. 7.6.1.20 INT_TOP_1
        21. 7.6.1.21 INT_TOP_2
        22. 7.6.1.22 INT_BUCK
        23. 7.6.1.23 TOP_STAT
        24. 7.6.1.24 BUCK_STAT
        25. 7.6.1.25 TOP_MASK_1
        26. 7.6.1.26 TOP_MASK_2
        27. 7.6.1.27 BUCK_MASK
        28. 7.6.1.28 SEL_I_LOAD
        29. 7.6.1.29 I_LOAD_2
        30. 7.6.1.30 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.1.2 Start and Stop Conditions

The TPS65653-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates the START and STOP conditions.

TPS65653-Q1 30190621.gifFigure 17. Start and Stop Sequences

The I2C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I2C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 18 shows the SDA and SCL signal timing for the I2C-compatible bus. See the Figure 1 for timing values.

TPS65653-Q1 30190619.gifFigure 18. I2C-Compatible Timing