ZHCSJI6 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
Address: 0x19
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
PGOOD_INT | Reserved | BUCK_INT | SYNC_CLK_INT | TDIE_SD_INT | TDIE_WARN_INT | OVP_INT | I_MEAS_INT |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7 | PGOOD_INT | R/W | 0 | Latched status bit indicating that the PGOOD pin has changed from active to inactive.
Write 1 to clear interrupt. |
6 | Reserved | R | 0 | |
5 | BUCK_INT | R | 0 | Interrupt indicating that Buck1 and/or Buck0 have a pending interrupt. The reason for the interrupt is indicated in INT_BUCK register.
This bit is cleared automatically when INT_BUCK register is cleared to 0x00. |
4 | SYNC_CLK_INT | R/W | 0 | Latched status bit indicating that the external clock has appeared or disappeared.
Write 1 to clear interrupt. |
3 | TDIE_SD_INT | R/W | 0 | Latched status bit indicating that the die junction temperature has exceeded the thermal shutdown level. The regulators have been disabled if they were enabled and GPO and GPO2 signals are driven low. The regulators cannot be enabled if this bit is active. The actual status of the thermal shutdown is indicated by TDIE_SD_STAT bit in TOP_STAT register.
Write 1 to clear interrupt. |
2 | TDIE_WARN_INT | R/W | 0 | Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TDIE_WARN_STAT bit in TOP_STAT register.
Write 1 to clear interrupt. |
1 | OVP_INT | R/W | 0 | Latched status bit indicating that the input voltage has exceeded the over-voltage detection level. The regulators have been disabled if they were enabled and GPO and GPO2 signals are driven low. The actual status of the over-voltage is indicated by OVP_STAT bit in TOP_STAT register.
Write 1 to clear interrupt. |
0 | I_MEAS_INT | R/W | 0 | Latched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt. |