ZHCSJI6 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
Address: 0x12
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Reserved | GPO2_OD | GPO2_EN_PIN_CTRL | GPO2_EN | Reserved | GPO_OD | GPO_EN_PIN_CTRL | GPO_EN |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7 | Reserved | R | 0 | |
6 | GP02_OD | R/W | X | GPO2 signal type when configured as General Purpose Output (CLKIN pin):
0 - Push-pull output (VANA level) 1 - Open-drain output |
5 | GPO2_EN_PIN_CTRL | R/W | X | Control for GPO2:
0 - Only GPO2_EN bit controls GPO2 1 - GPO2_EN bit AND EN pin control GPO2. |
4 | GPO2_EN | R/W | X | Output level of GPO2 signal (when configured as General Purpose Output):
0 - Logic low level 1 - Logic high level |
3 | Reserved | R | 0 | |
2 | GPO_OD | R/W | X | GPO signal type:
0 - Push-pull output (VANA level) 1 - Open-drain output |
1 | GPO_EN_PIN_CTRL | R/W | X | Control for GPO:
0 - Only GPO_EN bit controls GPO 1 - GPO_EN bit AND EN pin control GPO. |
0 | GPO_EN | R/W | X | Output level of GPO signal:
0 - Logic low level 1 - Logic high level |