Phased-array antennas and digital beamforming are key technologies that will boost the performance of future spaceborne radar imaging and broadband satellite communication systems. Digital beamforming, unlike analog beamforming, typically requires a set of data converters per antenna element. These converters need clocks with a specific defined phase relationship. This reference design shows how to generate low noise megahertz to gigahertz clock signals with defined and adjustable phase relationship. Clock phase even recovery is possible after single event strikes. JESD204B support is shown by operating two ADC12DJ3200QML-SP evaluation modules with their corresponding FPGA-based capturing platforms at 3.2 GHz with 10-ps board-to-board skew.
- Multichannel JESD204B-compliant clock tree
- Up to 15-GHz sample clock generation
- Less than 10-ps clock skew between channels
- Low phase noise (< 100 fs) clock signal
- Radiation hardened high-speed ADC, clocking, RF amplifiers and point-of-load power devices