SBAA543 July   2022 AFE7900 , AFE7920 , AFE7950


  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2JESD204C
    1. 2.1 Basic Review of JESD204C Protocol
    2. 2.2 Finding Optimal RBD for JESD204C
  5. 3JESD204B
    1. 3.1 Basic Review of JESD204B Protocol
    2. 3.2 Finding Optimal RBD for JESD204B
  6. 4Setting RBD in AFE79xx
    1. 4.1 Register Map
    2. 4.2 Setting RBD in Configuration Sequence
    3. 4.3 Finding Optimal RBD using CAPI
      1. 4.3.1 Use Case with 1 JESD Links
      2. 4.3.2 Use Case with 2 JESD Links
      3. 4.3.3 Use Case with 3 JESD Links
      4. 4.3.4 Use Case with 4 JESD Links
  7. 5Fixing Potential Alarms Related to RBD
    1. 5.1 RBD Alarm
    2. 5.2 SoEMB Close to LEMC Edge
    3. 5.3 Start of ILA Close to LMFC Edge
  8. 6References


This user's guide explains the methods to align multiple JESD204 receiver lanes in AFE79xx using Receive Buffer Delay (RBD). In practice, the JESD204 receiver requires buffering of various delays in the received lanes in order to ensure deterministic data throughout the data bus. A key feature in AFE79xx can optimize the buffer pointer through internal lane-to-lane skew and arrival of lane time stamps with respect to the JESD204 clock. The AFE79xx JESD204 receiver block has unique features to read the skew and arrival of lanes with respect to Local Multi Frame Clock (LMFC)/ Local Extended Multiblock Clock (LEMC) clock to help find the right RBD for the system.

The user's guide is structured as follows:

  • Understand the need for alignment across lanes.
  • Basic review of JESD protocol to help understand functioning of RBD.
  • Procedure to find the optimal RBD in AFE79xx with examples using C Application Process Interface (CAPI).
  • Potential RBD alarms and alarm recovery plans.