When there are two links, top JESD uses one link and bottom JESD uses another link. For the first link, the registers in page 0x16[2] are used and second link uses page 0x16[3].

1. For the first link, based on the lane0_f_counter_all_lane_ready in the first page, link0_rbd_m1 is set in the first page.
2. Similarly, for the second link, based on the lane0_f_counter_all_lane_ready in the second page, link0_rbd_m1 is set in the second page.

Example:

1. Link 1Read Page 0x16[2] : lane0_f_counter_all_lane_ready = 16 for link 1
   getAllLaneReady(afeInst,0,&laneAllReady)
   laneAllReady = 16 for link 1
   Link 2 Read Page 0x16[3] : lane0_f_counter_all_lane_ready = 36 for link 2
   getAllLaneReady(afeInst,2,&laneAllReady)
   laneAllReady = 36 for link 2
2. Obtain valid range of RBD.
   Link 1getGoodRbdRange(afeInst,0,&rbdMin,&rbdMax)
   rbdMin = 17
   rbdMax = 35 (Based on skew = 3, rbdMax = min(allLaneReady) + BufferDepth-10 = 16 - 3 + 32 - 10)
   Link 2getGoodRbdRange(afeInst,2,&rbdMin,&rbdMax)
   rbdMin = 37
   rbdMax = 55 (Based on skew = 3, rbdMax = min(allLaneReady) + BufferDepth - 10 = 36 - 3 + 32 - 10)
3. In this example, optimal value is chosen as rbdMin + 3 = 20 for link1 and 40 for link 2. In cases with multiple AFEs on a PCB, valid ranges can be looked at for all AFEs and optimal RBD can be chosen.
4. The optimal RBD is set and adcDacSync is run.
   Link 1
   setManualRbd(afeInst,0,20)
   Link 2
   setManualRbd(afeInst,2,40)
   adcDacSync(afeInst,1)
5. Read back link0_sysref_cnt_on_release_opportunity from the first page for link 1 and second page for link 2.
   Link 1getSysrefCntOnReleaseOpp(afeInst,0,&readVal)
   If readVal=1, optimal RBD is chosen as (20+1)%64 = 21
   Link 2getSysrefCntOnReleaseOpp(afeInst,2,&readVal)
   If readVal=1, optimal RBD is chosen as (40+1)%64 = 41
6. In the config, value of 21 is set for the link0_rbd_m1 in the first page and value for 41 is set for the link0_rbd_m1 in the second page.

   In Latte, sysParams.jesdRxRbd is set to [21,21,41,41]