This section provides a very brief review of JESD204B protocol, so as to understand terminologies related to setting the optimal RBD.

JESD204B implements 8b/10b encoding, where 8 bits of data are encoded into 10 bits of data to ensure DC balanced signal. A frame in JESD204B consists of ‘F’ number of octets. In Latte, F is specified as part of LMFSHd parameter definition for DAC as follows.

sysParams.LMFSHdTx

Further, ‘K’ number of frames are combined into a multiframe. The parameter ‘K’ is configurable in Latte - sysParams.jesdRxK. Typically, a value of 32 or 16 is used for K. In each multiframe, there will be F*K octets.

The JESD receiver uses a LMFC to correct for the skew between lanes. The LMFC period is equal to the multiframe period. For example,

Lane Rate = 9830.4 Gbps

LMFC clock frequency = 9830.4/10/F/K GHz

For F = 4 and K = 32, LMFC clock frequency can be calculated as 7.68 MHz.

To ensure that the processing clock LMFC, between the JESD204 transmitter and JESD204 receiver, are aligned at start-up of the system without drift or wander, a global system reference clock (SYSREF) provides the clock synchronization and alignment. The SYSREF frequency is an integer factor of LMFC frequency. The SYSREF is distributed throughout the JESD204 system in a time aligned, fixed delay manner throughout various temperature cycle and system restart cycle. Since SYSREF is essentially deterministic, the data transfer through the JESD204 link will also be deterministic.

To compensate for the lane-to-lane skew, the JESD204B receiver has an internal buffer to first absorb the skews amongst all the lanes, and then re-align the lanes at the output of the buffer upon the release of the buffer. This essentially created a zero-skew environment for data processing at the output the JESD204B receiver. This is highlighted in Figure 3-1.⁽¹⁾

The buffer and the release of the buffer is controlled by RBD, or receive buffer delay. Finding the optimal RBD value in a system that will work across various temperature and restart cycle is essential in the overall system stability.

There exists a SYNC signal from the JESD receiver to JESD transmitter, which is used to request synchronization characters such as K28.5 characters and indicate signal detection of the synchronization signal. Once the receiver detects consecutive K28.5 characters, the receiver de-asserts the SYNC~ signal. Once the transmitter detects a toggle in the SYNC pin, it moves to the Initial Lane Alignment (ILA) phase.

In the JESD204B transmitter, the start of ILA (shown in Figure 3-1) shall be initiated simultaneously across all lanes at a well-defined moment in time. The transition from /K/ character to /R/ character marks the start of ILA (highlighted in red in Figure 3-1). The ‘well-defined moment in time’ is a deterministic period of time from the LMFC edge.

In the JESD204B receiver, to align data across lanes, a buffer exists to hold all lane data for release simultaneously at a well-defined moment in time. The ‘well-defined moment in time’ for RX buffer release is a programmable number of steps after an active LMFC edge. This programmable number of steps is referred to as the RX Buffer Delay (RBD).