SBAA543 July   2022 AFE7900 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2JESD204C
    1. 2.1 Basic Review of JESD204C Protocol
    2. 2.2 Finding Optimal RBD for JESD204C
  5. 3JESD204B
    1. 3.1 Basic Review of JESD204B Protocol
    2. 3.2 Finding Optimal RBD for JESD204B
  6. 4Setting RBD in AFE79xx
    1. 4.1 Register Map
    2. 4.2 Setting RBD in Configuration Sequence
    3. 4.3 Finding Optimal RBD using CAPI
      1. 4.3.1 Use Case with 1 JESD Links
      2. 4.3.2 Use Case with 2 JESD Links
      3. 4.3.3 Use Case with 3 JESD Links
      4. 4.3.4 Use Case with 4 JESD Links
  7. 5Fixing Potential Alarms Related to RBD
    1. 5.1 RBD Alarm
    2. 5.2 SoEMB Close to LEMC Edge
    3. 5.3 Start of ILA Close to LMFC Edge
  8. 6References

4.3.3 Use Case with 3 JESD Links

In use-cases where there are 3 JESD links, there are two possibilities.

  1. Top JESD has two links, bottom JESD has one link.
  2. Top JESD has one link, bottom JESD has one link.

We discuss only the first case here, but the same procedure holds for the second case if the pages are switched around. For the CAPIs, for first case, the linkNo argument would be 0, 1, 2 for links 1, 2 and 3 respectively. For the second case, the linkNo argument would be 0, 2, 3 for links 1, 2 and 3 respectively.

  1. For the first link, based on the lane0_f_counter_all_lane_ready in the first page, link0_rbd_m1 is set in the first page.
  2. For the second link, based on the lane2_f_counter_all_lane_ready in the first page, link1_rbd_m1 is set in the first page.
  3. For the third link, based on the lane0_f_counter_all_lane_ready in the second page, link0_rbd_m1 is set in the second page.

Example:

  1. Link 1
    Read Page 0x16[2] : lane0_f_counter_all_lane_ready = 16 for link 1
    getAllLaneReady(afeInst,0,&laneAllReady)
    laneAllReady = 16 for link 1

    Link 2

    Read Page 0x16[2] : lane2_f_counter_all_lane_ready = 26 for link 2
    getAllLaneReady(afeInst,1,&laneAllReady)
    laneAllReady = 26 for link 2

    Link 3

    Read Page 0x16[3] : lane0_f_counter_all_lane_ready = 36 for link 3
    getAllLaneReady(afeInst,2,&laneAllReady)
    laneAllReady = 36 for link 3
  2. Obtain valid range of RBD.

    Link 1

    getGoodRbdRange(afeInst,0,&rbdMin,&rbdMax)
    rbdMin = 17
    rbdMax = 35 (Based on skew=3, rbdMax = min(allLaneReady) + BufferDepth - 10 = 16 - 3 + 32 - 10)

    Link 2

    getGoodRbdRange(afeInst,1,&rbdMin,&rbdMax)
    rbdMin = 27
    rbdMax =45 (Based on skew=3, rbdMax = min(allLaneReady) + BufferDepth - 10 = 26 - 3 + 32 - 10)

    Link 3

    getGoodRbdRange(afeInst,2,&rbdMin,&rbdMax)
    rbdMin = 37
    rbdMax = 55 (Based on skew=3, rbdMax = min(allLaneReady) + BufferDepth - 10 = 36 - 3 + 32 - 10)
  3. In this example, optimal value is chosen as rbdMin+3 = 20 for link1, 30 for link 2 and 40 for link 3. In cases with multiple AFEs on a PCB, valid ranges can be looked at for all AFEs and optimal RBD can be chosen.
  4. The optimal RBD is set and adcDacSync is run.

    Link 1

    setManualRbd(afeInst,0,20)

    Link 2

    setManualRbd(afeInst,1,30)

    Link 3

    setManualRbd(afeInst,2,40)
    adcDacSync(afeInst,1)
  5. Read back link0_sysref_cnt_on_release_opportunity from the first page for link 1, link1_sysref_cnt_on_release_opportunity from the first page for link 2 and link0_sysref_cnt_on_release_opportunity from second page for link 3.

    Link 1

    getSysrefCntOnReleaseOpp(afeInst,0,&readVal)
    If readVal = 1, optimal RBD is chosen as (20+1)%64 = 21

    Link 2

    getSysrefCntOnReleaseOpp(afeInst,1,&readVal)
    If readVal=1, optimal RBD is chosen as (30+1)%64 = 31

    Link 3

    getSysrefCntOnReleaseOpp(afeInst,2,&readVal)
    If readVal=1, optimal RBD is chosen as (40+1)%64 = 41
  6. In the config, value of 21 is set for the link0_rbd_m1 in the first page, value of 31 is set for the link1_rbd_m1 in the first page and value for 41 is set for the link0_rbd_m1 in the second page.

    In Latte, sysParams.jesdRxRbd is set to [21,31,41,41]