SBAA543 July   2022 AFE7900 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2JESD204C
    1. 2.1 Basic Review of JESD204C Protocol
    2. 2.2 Finding Optimal RBD for JESD204C
  5. 3JESD204B
    1. 3.1 Basic Review of JESD204B Protocol
    2. 3.2 Finding Optimal RBD for JESD204B
  6. 4Setting RBD in AFE79xx
    1. 4.1 Register Map
    2. 4.2 Setting RBD in Configuration Sequence
    3. 4.3 Finding Optimal RBD using CAPI
      1. 4.3.1 Use Case with 1 JESD Links
      2. 4.3.2 Use Case with 2 JESD Links
      3. 4.3.3 Use Case with 3 JESD Links
      4. 4.3.4 Use Case with 4 JESD Links
  7. 5Fixing Potential Alarms Related to RBD
    1. 5.1 RBD Alarm
    2. 5.2 SoEMB Close to LEMC Edge
    3. 5.3 Start of ILA Close to LMFC Edge
  8. 6References

2.1 Basic Review of JESD204C Protocol

This section provides a very brief review of JESD204C protocol, so as to understand terminologies related to setting the optimal RBD.

JESD204C implements 64b/66b encoding. To each set of eight octets (64 bits), two pilot bits called sync header are inserted. The 2 bits in sync header are invert of each other, which means the sync header can only be 10 or 01. With this unique property of sync header, the JESD receiver identifies and locks on to the 66-bit boundary. These 66 bits are termed as blocks.

The blocks are then built into a multiblock, that consists of 32 blocks, as shown in Figure 2-1(1). The sync header SH0 to SH31 follow a pattern as described in the protocol, which helps the JESD receiver lock onto the multiblock boundary.

Figure 2-1 JESD204C Multiblock Structure

Further, ‘E’ number of multiblocks are combined into a extended multiblock. The parameter ‘E’ is configurable in Latte -

sysParams.jesdRxK

Typically, for 16-bit data packing (that is, typical F = 1, 2, 4, or 8 cases), E is set to 1. For 12-bit data packing (that is, F = 3 or F = 6 cases) patterns E is set to 3, so that each extended multiblock contains an integer number of samples and integer number of frames. The information stored in sync header, specifically SH22, is used to identify the end of an extended multiblock.

The JESD receiver uses a LEMC to correct for the skew between lanes. The LEMC period is equal to the extended multi-block period. For example,

Lane Rate = 24.33024 Gbps
LEMC clock frequency = 24.33024/66/32/E GHz
For E = 1, LEMC clock frequency can be calculated as 11.52 MHz

To ensure that the processing clock LEMC, between the JESD204 transmitter and JESD204 receiver, are aligned at start-up of the system without drift or wander, a global system reference clock (SYSREF) provides the clock synchronization and alignment. The SYSREF frequency is an integer factor of LEMC frequency. The SYSREF is distributed throughout the JESD204 system in a time aligned, fixed delay manner throughout various temperature cycle and system restart cycle. Since SYSREF is essentially deterministic, the data transfer through the JESD204 link will also be deterministic.

Figure 2-2 Timing Diagram of JESD204C Depicting RBD Functionality

To compensate for the lane-to-lane skew, the JESD204C receiver has an internal buffer to first absorb the skews amongst all the lanes, and then re-align the lanes at the output of the buffer upon the release of the buffer. This essentially created a zero-skew environment for data processing at the output the JESD204C receiver. This is highlighted in Figure 2-2(1).

The buffer and the release of the buffer is controlled by RBD, or receive buffer delay. Finding the optimal RBD value in a system that will work across various temperature and restart cycle is essential in the overall system stability.

In the JESD204C transmitter, the Start of Extended Multi Block (SoEMB as shown in Figure 2-2) shall be initiated simultaneously across all lanes at a well-defined moment in time. The ‘well-defined moment in time’ is a deterministic period of time from the LEMC edge.

In the JESD204C receiver, to align data across lanes, a buffer exists to hold all lane data for release simultaneously at a well-defined moment in time. The ‘well-defined moment in time’ for RX buffer release is a programmable number of steps after an active LEMC edge. This programmable number of steps is referred to as the Receive Buffer Delay (RBD).

1.

Parts of figures were based on JEDEC JESD204C standard, Figure 5 and Figure 50. Copyright JEDEC. Modifications have not been approved by and do not reflect the views of JEDEC.

1.

Parts of figures were based on JEDEC JESD204C standard, Figure 5 and Figure 50. Copyright JEDEC. Modifications have not been approved by and do not reflect the views of JEDEC.