SBAA543 July   2022 AFE7900 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2JESD204C
    1. 2.1 Basic Review of JESD204C Protocol
    2. 2.2 Finding Optimal RBD for JESD204C
  5. 3JESD204B
    1. 3.1 Basic Review of JESD204B Protocol
    2. 3.2 Finding Optimal RBD for JESD204B
  6. 4Setting RBD in AFE79xx
    1. 4.1 Register Map
    2. 4.2 Setting RBD in Configuration Sequence
    3. 4.3 Finding Optimal RBD using CAPI
      1. 4.3.1 Use Case with 1 JESD Links
      2. 4.3.2 Use Case with 2 JESD Links
      3. 4.3.3 Use Case with 3 JESD Links
      4. 4.3.4 Use Case with 4 JESD Links
  7. 5Fixing Potential Alarms Related to RBD
    1. 5.1 RBD Alarm
    2. 5.2 SoEMB Close to LEMC Edge
    3. 5.3 Start of ILA Close to LMFC Edge
  8. 6References

4.1 Register Map

The addresses of all registers referred to in this user's guide are described in Table 4-1. There exists two pages of registers for DAC JESD block. The page select to choose appropriate page is ‘dac_jesd’ (0x16[3:2]).

Table 4-1 Register Map
Register Name Read/Write Address
dac_jesd R/W 0x16[3:2]
lane0_f_counter_any_lane_ready R 0x89[7:0], 0x88[7:0]
lane1_f_counter_any_lane_ready R 0x8B[7:0], 0x8A[7:0]
lane2_f_counter_any_lane_ready R 0x8D[7:0], 0x8C[7:0]
lane3_f_counter_any_lane_ready R 0x8F[7:0], 0x8E[7:0]
lane0_f_counter_all_lane_ready R 0x91[7:0], 0x90[7:0]
lane1_f_counter_all_lane_ready R 0x93[7:0], 0x92[7:0]
lane2_f_counter_all_lane_ready R 0x95[7:0], 0x94[7:0]
lane3_f_counter_all_lane_ready R 0x97[7:0], 0x96[7:0]
lane0_skew R 0x13C[4:0]
lane1_skew R 0x13D[4:0]
lane2_skew R 0x13E[4:0]
lane3_skew R 0x13F[4:0]
link0_rbd_m1 R/W 0x69[7:0], 0x68[7:0]
link1_rbd_m1 R/W 0x6B[7:0], 0x6A[7:0]
link0_init_f_counter R/W 0x71[7:0]
link1_init_f_counter R/W 0x73[7:0]
link0_init_o_counter R/W 0x70[7:0]
link1_init_o_counter R/W 0x72[7:0]
alarms R 0x11F[8:0], 0x11E[8:0], 0x11D[8:0], 0x11C[8:0], 0x11B[8:0], 0x11A[8:0], 0x119[8:0], 0x118[8:0],
link0_sysref_cnt_on_release_opportunity R 0x98[3:0]
link1_sysref_cnt_on_release_opportunity R 0x98[7:4]
link0_buffer_depth R/W 0x6E[3:0]
link1_buffer_depth R/W 0x6F[3:0]