The XO input has amplitude and frequency monitors to help qualify the input before the input can be used to lock the APLLs.

The XO amplitude detector clears the LOS (loss-of-signal) flag when the differential input voltage swing (peak-to-peak) is greater than the minimum threshold selected by the registers (400, 600, or 800 mVpp nominal). The same threshold applies also for a single-ended LVCMOS input with the non-driven input pin pulled to ground. If the input clock does not meet the amplitude threshold, the amplitude detector is set the LOS flag and disqualify the input.

The XO frequency detector clears the LOS_FDET flag when the input frequency is detected within the range of about 10 MHz to 90 MHz. Above 90 MHz, the frequency detector must be bypassed for proper operation. The XO frequency monitor uses a RC-based detector and cannot precisely detect if the XO input clock has sufficient frequency stability to provide successful VCO calibration during the PLL start-up when the external XO clock has a slow or delayed start-up behavior. See Slow or Delayed XO Start-Up for more information.

The XO monitors can be bypassed through registers, so the input is always considered valid by the PLL control state machines. The XO LOS status flags can be observed through the status pins and the status bits. The XO LOS signal from the status pin is the logic-OR combination of both the amplitude and frequency monitor flags.