ZHCSG76A April   2017  – March 2025 INA233

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Accuracy Analog-to-Digital Convertor (ADC)
      2. 6.3.2 Interleaved Power Calculation
      3. 6.3.3 Power Accumulator and Energy Measurement
      4. 6.3.4 I2C-, SMBus-, and PMBus-Compatible Digital Interface
      5. 6.3.5 Multiple Fault Event Reporting
    4. 6.4 Device Functional Modes
      1. 6.4.1 Continuous Verses Triggered Operation
      2. 6.4.2 Device Shutdown
      3. 6.4.3 Averaging and Conversion Time Considerations
      4. 6.4.4 Filtering and Input Considerations
    5. 6.5 Programming
      1. 6.5.1 Default Settings
      2. 6.5.2 Calibration Register and Scaling
      3. 6.5.3 Reading and Writing Telemetry Data and Warning Thresholds
      4. 6.5.4 Reading Telemetry Data and Warning Thresholds
        1. 6.5.4.1 Writing Telemetry Data and Warning Thresholds
      5. 6.5.5 System-Level Calibration With MFR_CALIRATION Command
      6. 6.5.6 Bus Overview
        1. 6.5.6.1 Serial Bus Address
        2. 6.5.6.2 Serial Interface
        3. 6.5.6.3 Writing to and Reading From the INA233
          1. 6.5.6.3.1 Packet Error Checking
          2. 6.5.6.3.2 Bus Timing Requirements
        4. 6.5.6.4 SMBus Alert Response
    6. 6.6 Register Maps
      1. 6.6.1 PMBus Command Support
      2. 6.6.2 Standard PMBus Commands
        1. 6.6.2.1  CLEAR_FAULTS (03h)
        2. 6.6.2.2  RESTORE_DEFAULT_ALL (12h)
        3. 6.6.2.3  CAPABILITY (19h)
        4. 6.6.2.4  IOUT_OC_WARN_LIMIT (4Ah) [default = 01111111 11111000]
        5. 6.6.2.5  VIN_OV_WARN_LIMIT (57h) [default = 01111111 11111000]
        6. 6.6.2.6  VIN_UV_WARN_LIMIT (58h) [default = 00000000 00000000]
        7. 6.6.2.7  PIN_OP_WARN_LIMIT (6Bh) [default = 11111111 11110000]
        8. 6.6.2.8  STATUS_BYTE (78h)
        9. 6.6.2.9  STATUS_WORD (79h)
        10. 6.6.2.10 STATUS_IOUT (7Bh)
        11. 6.6.2.11 STATUS_INPUT (7Ch)
        12. 6.6.2.12 STATUS_CML (7Eh)
        13. 6.6.2.13 STATUS_MFR_SPECIFIC (80h)
        14. 6.6.2.14 READ_EIN (86h)
        15. 6.6.2.15 READ_VIN (88h)
        16. 6.6.2.16 READ_IIN (89h)
        17. 6.6.2.17 READ_VOUT (8Bh)
        18. 6.6.2.18 READ_IOUT (8Ch, R)
        19. 6.6.2.19 READ_POUT (96h, R)
        20. 6.6.2.20 READ_PIN (97h, R)
        21. 6.6.2.21 MFR_ID (99h)
        22. 6.6.2.22 MFR_MODEL (9Ah)
        23. 6.6.2.23 MFR_REVISION (9Bh)
      3. 6.6.3 Manufacturer-Specific PMBus Commands
        1. 6.6.3.1 MFR_ADC_CONFIG (D0h) [default = 01000001 00100111]
        2. 6.6.3.2 MFR_READ_VSHUNT (D1h) [default = 00000000 00000000]
        3. 6.6.3.3 MFR_ALERT_MASK (D2h) [default = XXXXXXXX 11110000]
        4. 6.6.3.4 MFR_CALIBRATION (D4h) [default = 00000000 00000001]
        5. 6.6.3.5 MFR_DEVICE_CONFIG (D5h) [default = 00000010]
        6. 6.6.3.6 5.1.1 CLEAR_EIN (D6h)
        7. 6.6.3.7 TI_MFR_ID (E0h) [value = 01010100 01001001]
        8. 6.6.3.8 TI_MFR_MODEL (E1h) [value = 00110011 00110011]
        9. 6.6.3.9 TI_MFR_REVISION (E2h) [value = 01000001 00110000]
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Programming the Calibration Register
        2. 7.2.2.2 Calculating PMBus Coefficients
        3. 7.2.2.3 Programming Warning Thresholds
        4. 7.2.2.4 Calculating Returned Telemetry Values
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
6.5.6.3.2 Bus Timing Requirements

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. Figure 6-8 shows a timing diagram for the bus and Table 6-3 lists the bus timing definitions.

INA233 Bus Timing DiagramFigure 6-8 Bus Timing Diagram
Table 6-3 Bus Timing Definitions(1)
MINMAXUNIT
f(SCL)SCL operating frequency10400kHz
t(BUF)Bus free time between STOP and START conditions0.6µs
t(HDSTA)Hold time after a repeated START condition.
After this period, the first clock is generated.		0.6µs
t(SUSTA)Repeated START condition setup time0.6µs
t(SUSTO)STOP condition setup time0.6µs
t(HDDAT)Data hold time0ns
t(SUDAT)Data setup time100ns
t(LOW)SCL clock low period1.3µs
t(HIGH)SCL clock high period0.650µs
tFData fall time300ns
tFClock fall time300ns
tRClock rise time300ns
(1) Values are based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and are not production tested.