TIDUEW7 May   2020

 

  1.    Description
  2.    Resources
  3.    Features
  4.    Applications
  5.    Design Images
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Processor – i.MX 6ULL Applications Processor
      2. 2.2.2 i.MX 6ULL Memory Interfaces
        1. 2.2.2.1 DDR3L
        2. 2.2.2.2 Quad SPI NOR Flash
        3. 2.2.2.3 eMMC iNAND
        4. 2.2.2.4 SD Card Connector
      3. 2.2.3 USB to UART Converter
      4. 2.2.4 USB Ports
      5. 2.2.5 LCD Screen Connector
      6. 2.2.6 JTAG Header
      7. 2.2.7 USB2ANY Header
      8. 2.2.8 Functional Switches and Status LEDs
      9. 2.2.9 GPIO Expansion Connector
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS6521815 - Power Management IC
      2. 2.3.2 DP83849I - Dual Ethernet PHY
      3. 2.3.3 INA3221 - Current Monitor
      4. 2.3.4 Reset Scheme
      5. 2.3.5 TPS2054B, TPS22964C - Auxiliary Load Switches
    4. 2.4 System Design Theory
      1. 2.4.1 Power Estimation
      2. 2.4.2 Power Sequencing
      3. 2.4.3 I2C Device Chain
      4. 2.4.4 Clock Scheme
      5. 2.4.5 BOOT Configuration
      6. 2.4.6 PCB Floor Planning
  8. 3Getting Started, Testing Setup, and Test Results
    1. 3.1 Getting Started with Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 On-board LED Information
      2. 3.1.2 Software
        1. 3.1.2.1 Booting of TIDA-050043
        2. 3.1.2.2 Example Linux Commands for Testing TIDA-050043
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 CAD Files
    4. 4.4 Gerber Files
    5. 4.5 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
    2. 6.2 Third-Party Products Disclaimer

2.2.4 USB Ports

This design uses the processor's two USB interfaces, where the primary USB OTG1 interface connects directly to the micro-AB port and USB OTG2 acts as a host only, connecting to a USB Hub. The USB2517I is a 7-port USB hub that multiplexes the USB data from OTG2 and distributes the data to 5 Type-A receptacles. The block diagram shows both USB HUB and OTG interfacing with the processor. The wiring of the USB interfaces is shown in Figure 7.

DESCRIPTION MFG. PART NUMBER
USB Hub Section
Conn, USB 2.0, Type-A, Receptacle, 1x1, Shielded, RA, TH TE Connectivity 1-1734775-1
Conn, USB Type-A Receptacle, 2x1, Shielded, Stacked, RA, TH TE Connectivity ZX62D-AB- 5P8(30)
Filter, Choke coil, CM, 90E, 330mA, Signal Line, SMD Murata DLW21HN900SQ2L
IC, TPS2054B, Quad Current-Limited Power-Distribution Switch, SOIC-16 Texas Instruments TPS2054BDR
IC, USB2517I, USB HUB, 7-Ports, QFN-64 Microchip USB2517I-JZX
USB OTG Section
Conn, USB 2.0 Micro AB Receptacle, 1x1, Shielded, RA, SMD FCI - Amphenol ICC 10104111-0001LF
Filter, Choke coil, CM, 90E, 330mA, Signal Line, SMD Murata DLW21HN900SQ2L
IC, MIC2026, Dual Channel Power Distribution Switch, SOIC-8 Microchip MIC2026-1YM
Figure 7. USB InterfaceTIDA-050043 tida-050043-usb-hub-tiduew7.gif