SWRZ101B December   2021  – December 2023 AM2732 , AM2732-Q1

 

  1.   1
  2.   Abstract
  3. 1Silicon Usage Notes and Advisories Matrices
    1.     Devices Supported
  4. 2 Usage Notes and Advisories
    1.     Silicon Usage Notes
      1.      i2293
      2.      i2295
      3.      i2300
      4.      i2324
      5.      i2364
      6.      i2389
      7.      i2390
    2.     Silicon Advisories
      1.      i2162
      2.      i2288
      3.      i2289
      4.      i2294
      5.      i2297
      6.      i2298
      7.      i2299
      8.      i2301
      9.      i2302
      10.      i2309
      11.      i2315
      12.      i2318
      13.      i2329
      14.      i2336
      15.      i2337
      16.      i2338
      17.      i2339
      18.      i2340
      19.      i2341
      20.      i2342
      21.      i2344
      22.      i2345
      23.      i2387
      24.      i2392
      25.      i2394
      26.      i2386
  5.   Trademarks
  6. 3Revision History

i2338

MibSPI: Spurious RX DMA REQ From a Peripheral Mode MibSPI

Details:

A spurious DMA request could be generated even when the SPI Peripheral is not transferring data in the following condition sequence:

  • The MIBSPI is configured in standard (non-multibuffered) SPI mode, as a Peripheral
  • The DMAREQEN bit (SPIINT0.16) is set to enable DMA requests
  • The Chip Select (nSCS) pin is in an active state, but no transfers are active
  • The SPI is disabled by clearing the SPIEN (SPIGCR1.24) bit from '1' to '0'

The above sequence triggers a false request pulse on the Receive DMA Request as soon as the SPIEN bit is cleared from '1' to '0'.

Workaround(s):

Whenever disabling the SPI, by clearing the SPIEN bit (SPIGCR1.24), first clear the DMAREQEN bit (SPIINT0.16) to '0', and then, clear the SPIEN bit.