1 Silicon Usage Notes and Advisories Matrices

Table 1-1 lists all usage notes and the applicable silicon revision(s). Table 1-2 lists all advisories, modules affected, and the applicable silicon revision(s).

Table 1-1 Silicon Usage Notes Matrix

NUMBER	TITLE	SILICON REVISIONS AFFECTED
NUMBER	TITLE	AM273x 1.0	AM273x 1.1	AM273x 1.2
Aurora	i2293 - Aurora Interface does not operate at maximum rated frequency if Clock lane is required or in Bypass mode of operation	YES	YES	YES
Clocks	i2324 - No synchronizer present between GCM and GCD status signals	YES	YES	YES
DSP	i2295 - Memory filter protection within DSP cannot filter access based on PrivID	YES	YES	YES
ESM	i2300 - ESM: nerror gets asserted in safety-enabled test cases when warm reset is asserted multiple times	YES	YES	YES
QSPI	i2364 - Access to address beyond 8MB is not supported in mem map mode	YES	YES	YES
PLL	i2389 - Recommended PLL configuration if locked below 1GHz	YES	YES	YES
	i2390 - Recommended HWA memInit Sequence	YES	YES	YES

Table 1-2 Silicon Advisories Matrix

MODULE	DESCRIPTION	SILICON REVISIONS AFFECTED
MODULE	DESCRIPTION	AM273x 1.0	AM273x 1.1	AM273x 1.2
Aurora	i2299 - Aurora IP first pattern should not be sync	YES	YES	YES
	i2344 - Valid udp size range is AURORA_TX_UDP_SIZE > 4	YES	YES	YES
CPSW	i2345 - Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks	YES	YES	YES
CSI	i2297 - CSI Careabouts	YES	YES	YES
DMM	i2315 - DMM Careabouts while in Trace mode	YES	YES	YES
	i2318 - DMM cannot write to region which only supports privilege mode writes	YES	YES	YES
DSP	i2298 - DSP PBIST Reset changing DSP L2 clock	YES	YES	YES
	i2341 - Unallocated space access to DSP L2 - DSP IP is not blocking access to reserved space causing aliasing and L2 parity error	YES	YES	YES
DSS	i2289 - Unaligned access from DSS CM4 could cause data integrity failure and hang	YES	YES	YES
EDMA	i2288 - EDMA transfer that spans M1+M2 memories of HWA could result in data corruption	YES	YES	YES
L3	i2294 - Subsequent memory initialization configuration of L3 Bank D will not trigger a memory initialization	YES	YES	YES
MDO	i2301 - MDO: SW marker inserted at FIFO threshold location gets missed	YES	YES	YES
	i2302 - MDO: Issue seen in potential interoperability with receiver supporting on Strict Alignment User Flow Control Stripping during overflow message transmission in Aurora 64B/66B Protocol.	YES	YES	YES
	i2309 - MDO: HWA vbusm2ram sniffer address allocation logic is incorrect	YES	YES	YES
	i2329 - MDIO interface corruption (CPSW and PRU-ICSS)	YES	YES	YES
MiBSPI	i2336 - MibSPI in Peripheral Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1	YES	YES	YES
	i2338 - Spurious RX DMA REQ From a Peripheral Mode MibSPI	YES	YES	YES
	i2339 - MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After Reading	YES	YES	YES
	i2340 - MibSPI RAM ECC is not read Correctly in DIAG Mode	YES	YES	YES
RAM	i2342 - 2D Stats sample value RAM processor write back issue during FFT execution on HWA	YES	YES	YES
R5FSS	i2162 - The Same Interrupt Cannot be Nested Back-2-Back Within Another Interrupt	YES	YES	YES
SPI	i2337 - A Data Length Error is Generated Repeatedly in Peripheral Mode When IO Loopback is Enabled	YES	YES	YES
PLL	i2387 - GCM circuit glitch during clock source switch	YES	YES	YES
	i2392 - Race condition in mem-init capture registers resulting in events miss	YES	YES	YES
	i2394 - Race condition in interrupt and error aggregator capture registers resulting in events miss	YES	YES	YES
CRC	i2386 - CRC 8-bit data width and CRC8-SAE-J1850 and CRC8-H2F possible use in CAN module is not supported	YES	YES	YES