Details

Any EDMA transfer that spans M1+M2 memories of HWA may result in data corruption without any notification of error from the SoC.

As per TPTC IP Spec, a TR is supposed to access a single target end point. M0/M1 memory banks of HWA are available via single target point and M2/M3 memory banks of HWA are available as another target point (different from that of M0/M1). Hence if a single TR is used to access a buffer spanning M1 and M2 memories of the HWA (i.e. a single buffer spanning 2 different target points), the spec is not being adhered to. This errata is explicitly highlighting this spec requirement.

Workaround

Split the access into 2 TRs so that a single TR does not span M1+M2. The 2 TRs can be chained.