SWRZ101B December 2021 – December 2023 AM2732 , AM2732-Q1
Subsequent memory initialization configuration of L3 Bank D will not trigger a memory initialization
Memory initialization for DSS_L3 Bank D is not a write pulse high but read-write bit DSS_CTRL::DSS_L3RAM_MEMINIT_START::L3RAM3_MEMINIT_START
To trigger a subsequent memory initialization, write 0x0 to the field before writing 0x1 to trigger memory initialization.