SPRUJD3A July   2025  – October 2025 F28E120SB , F28E120SC

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit (FPU)
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Power-On Reset (POR)
      4. 3.4.4  Brown-Out-Reset (BOR)
      5. 3.4.5  Watchdog Reset (WDRS)
      6. 3.4.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.4.7  Debugger Reset (SYSRS)
      8. 3.4.8  DCSM Safe Code Copy Reset (SCCRESET)
      9. 3.4.9  Simulate External Reset (SIMRESET.XRS)
      10. 3.4.10 Simulate CPU Reset (SIMRESET_CPU1RS)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
      6. 3.5.6 PIE Interrupt Priority
        1. 3.5.6.1 Channel Priority
        2. 3.5.6.2 Group Priority
      7. 3.5.7 System Error
      8. 3.5.8 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection Logic
        2. 3.6.3.2 Flash Uncorrectable ECC Error
        3. 3.6.3.3 Software-Forced Error
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (SYSOSC)
        2. 3.7.1.2 Backup Wide-Range Oscillator (WROSC)
        3. 3.7.1.3 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low Power-Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
    11. 3.11 Memory Controller Module
      1. 3.11.1 Dedicated RAM (Mx RAM)
      2. 3.11.2 Global Shared RAM (GSx RAM)
      3. 3.11.3 Access Arbitration
      4. 3.11.4 Memory Error Detection, Correction, and Error Handling
        1. 3.11.4.1 Error Detection and Correction
        2. 3.11.4.2 Error Handling
      5. 3.11.5 Application Test Hooks for Error Detection and Correction
      6. 3.11.6 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 System Control Register Configuration Restrictions
    14. 3.14 Software
      1. 3.14.1 SYSCTL Examples
        1. 3.14.1.1 Missing clock detection (MCD)
        2. 3.14.1.2 XCLKOUT (External Clock Output) Configuration
    15. 3.15 SYSCTRL Registers
      1. 3.15.1  SYSCTRL Base Address Table
      2. 3.15.2  CPUTIMER_REGS Registers
      3. 3.15.3  PIE_CTRL_REGS Registers
      4. 3.15.4  WD_REGS Registers
      5. 3.15.5  NMI_INTRUPT_REGS Registers
      6. 3.15.6  XINT_REGS Registers
      7. 3.15.7  SYNC_SOC_REGS Registers
      8. 3.15.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.15.9  DEV_CFG_REGS Registers
      10. 3.15.10 CLK_CFG_REGS Registers
      11. 3.15.11 CPU_SYS_REGS Registers
      12. 3.15.12 SYS_STATUS_REGS Registers
      13. 3.15.13 MEM_CFG_REGS Registers
      14. 3.15.14 MEMORY_ERROR_REGS Registers
      15. 3.15.15 ROM_WAIT_STATE_REGS Registers
      16. 3.15.16 TEST_ERROR_REGS Registers
      17. 3.15.17 UID_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Secure Flash Boot
        1. 4.7.4.1 Secure Flash CPU1 Linker File Example
      5. 4.7.5  Memory Maps
        1. 4.7.5.1 Boot ROM Memory Maps
        2. 4.7.5.2 Reserved RAM Memory Maps
      6. 4.7.6  ROM Tables
      7. 4.7.7  Boot Modes and Loaders
        1. 4.7.7.1 Boot Modes
          1. 4.7.7.1.1 Flash Boot
          2. 4.7.7.1.2 RAM Boot
          3. 4.7.7.1.3 Wait Boot
        2. 4.7.7.2 Bootloaders
          1. 4.7.7.2.1 SCI Boot Mode
          2. 4.7.7.2.2 SPI Boot Mode
          3. 4.7.7.2.3 I2C Boot Mode
          4. 4.7.7.2.4 Parallel Boot Mode
      8. 4.7.8  GPIO Assignments
      9. 4.7.9  Secure ROM Function APIs
      10. 4.7.10 Clock Initializations
      11. 4.7.11 Boot Status Information
        1. 4.7.11.1 Booting Status
      12. 4.7.12 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Wrapper
    4. 6.4  Flash and OTP Memory Performance
    5. 6.5  Flash Read Interface
      1. 6.5.1 C28x-Flash Read Interface
        1. 6.5.1.1 Standard Read Mode
        2. 6.5.1.2 Prefetch Mode
        3. 6.5.1.3 Data Cache
        4. 6.5.1.4 Flash Read Operation
    6. 6.6  Flash Erase and Program
      1. 6.6.1 Erase
      2. 6.6.2 Program
      3. 6.6.3 Verify
    7. 6.7  Error Correction Code (ECC) Protection
      1. 6.7.1 Single-Bit Data Error
      2. 6.7.2 Uncorrectable Error
      3. 6.7.3 ECC Logic Self Test
    8. 6.8  Reserved Locations Within Flash and OTP
    9. 6.9  Migrating an Application from RAM to Flash
    10. 6.10 Procedure to Change the Flash Control Registers
    11. 6.11 Software
      1. 6.11.1 FLASH Examples
        1. 6.11.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
    12. 6.12 FLASH Registers
      1. 6.12.1 FLASH Base Address Table
      2. 6.12.2 FLASH_CTRL_REGS Registers
      3. 6.12.3 FLASH_ECC_REGS Registers
  9. 7 Dual-Clock Comparator (DCC)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 Block Diagram
    2. 7.2 Module Operation
      1. 7.2.1 Configuring DCC Counters
      2. 7.2.2 Single-Shot Measurement Mode
      3. 7.2.3 Continuous Monitoring Mode
      4. 7.2.4 Error Conditions
    3. 7.3 Interrupts
    4. 7.4 Software
      1. 7.4.1 DCC Examples
        1. 7.4.1.1 DCC Single shot Clock verification
        2. 7.4.1.2 DCC Single shot Clock measurement
        3. 7.4.1.3 DCC Continuous clock monitoring
        4. 7.4.1.4 DCC Continuous clock monitoring
        5. 7.4.1.5 DCC Detection of clock failure
    5. 7.5 DCC Registers
      1. 7.5.1 DCC Base Address Table
      2. 7.5.2 DCC_REGS Registers
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital Inputs on ADC Pins (AIOs)
    4. 8.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 8.5  Digital General-Purpose I/O Control
    6. 8.6  Input Qualification
      1. 8.6.1 No Synchronization (Asynchronous Input)
      2. 8.6.2 Synchronization to SYSCLKOUT Only
      3. 8.6.3 Qualification Using a Sampling Window
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Open-Drain Configuration Requirements
    10. 8.10 Software
      1. 8.10.1 GPIO Examples
        1. 8.10.1.1 Device GPIO Setup
        2. 8.10.1.2 Device GPIO Toggle
        3. 8.10.1.3 Device GPIO Interrupt
        4. 8.10.1.4 External Interrupt (XINT)
      2. 8.10.2 LED Examples
    11. 8.11 GPIO Registers
      1. 8.11.1 GPIO Base Address Table
      2. 8.11.2 GPIO_CTRL_REGS Registers
      3. 8.11.3 GPIO_DATA_REGS Registers
      4. 8.11.4 GPIO_DATA_READ_REGS Registers
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 MCPWM and GPIO Output X-BAR
      1. 9.2.1 MCPWM X-BAR
        1. 9.2.1.1 MCPWM X-BAR Architecture
      2. 9.2.2 GPIO Output X-BAR
        1. 9.2.2.1 GPIO Output X-BAR Architecture
      3. 9.2.3 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 PWM_XBAR_REGS Registers
      5. 9.3.5 OUTPUT_XBAR_REGS Registers
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 Channel Priority
      1. 10.5.1 Round-Robin Mode
      2. 10.5.2 Channel 1 High-Priority Mode
    6. 10.6 Overrun Detection Feature
    7. 10.7 Software
      1. 10.7.1 DMA Examples
        1. 10.7.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.7.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    8. 10.8 DMA Registers
      1. 10.8.1 DMA Base Address Table
      2. 10.8.2 DMA_REGS Registers
      3. 10.8.3 DMA_CH_REGS Registers
  13. 11Analog Subsystem
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Digital Inputs on ADC Pins (AIOs)
    3. 11.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    4. 11.4 Analog Pins and Internal Connections
    5. 11.5 ASBSYS Registers
      1. 11.5.1 ASBSYS Base Address Table
      2. 11.5.2 ANALOG_SUBSYS_REGS Registers
  14. 12Analog-to-Digital Converter (ADC)
    1. 12.1  Introduction
      1. 12.1.1 Features
      2. 12.1.2 ADC Related Collateral
      3. 12.1.3 Block Diagram
    2. 12.2  ADC Configurability
      1. 12.2.1 ADC Clock Configuration
      2. 12.2.2 Resolution
      3. 12.2.3 Voltage Reference
        1. 12.2.3.1 External Reference Mode
        2. 12.2.3.2 Internal Reference Mode
        3. 12.2.3.3 Selecting Reference Mode
      4. 12.2.4 Signal Mode
        1. 12.2.4.1 Expected Conversion Results
        2. 12.2.4.2 Interpreting Conversion Results
    3. 12.3  SOC Principle of Operation
      1. 12.3.1 SOC Configuration
      2. 12.3.2 Trigger Operation
        1. 12.3.2.1 Trigger Repeaters
          1. 12.3.2.1.1 Oversampling Mode
          2. 12.3.2.1.2 Re-trigger Spread
          3. 12.3.2.1.3 Trigger Repeater Configuration
            1. 12.3.2.1.3.1 Register Shadow Updates
          4. 12.3.2.1.4 Re-Trigger Logic
          5. 12.3.2.1.5 Multi-Path Triggering Behavior
      3. 12.3.3 ADC Acquisition (Sample and Hold) Window
      4. 12.3.4 Sample Capacitor Reset
      5. 12.3.5 ADC Input Models
      6. 12.3.6 Channel Selection
    4. 12.4  SOC Configuration Examples
      1. 12.4.1 Single Conversion from MCPWM Trigger
      2. 12.4.2 Multiple Conversions from CPU Timer Trigger
      3. 12.4.3 Software Triggering of SOCs
    5. 12.5  ADC Conversion Priority
    6. 12.6  EOC and Interrupt Operation
      1. 12.6.1 Interrupt Overflow
      2. 12.6.2 Continue to Interrupt Mode
      3. 12.6.3 Early Interrupt Configuration Mode
    7. 12.7  Post-Processing Blocks
      1. 12.7.1 PPB Offset Correction
      2. 12.7.2 PPB Error Calculation
      3. 12.7.3 PPB Limit Detection and Zero-Crossing Detection
    8. 12.8  Opens/Shorts Detection Circuit (OSDETECT)
      1. 12.8.1 Open Short Detection Implementation
      2. 12.8.2 Detecting an Open Input Pin
      3. 12.8.3 Detecting a Shorted Input Pin
    9. 12.9  Power-Up Sequence
    10. 12.10 ADC Calibration
      1. 12.10.1 ADC Zero Offset Calibration
    11. 12.11 ADC Timings
      1. 12.11.1 ADC Timing Diagrams
      2. 12.11.2 Post-Processing Block Timings
    12. 12.12 Additional Information
      1. 12.12.1 Choosing an Acquisition Window Duration
      2. 12.12.2 Result Register Mapping
      3. 12.12.3 Internal Temperature Sensor
      4. 12.12.4 Designing an External Reference Circuit
      5. 12.12.5 ADC-DAC Loopback Testing
      6. 12.12.6 Internal Test Mode
    13. 12.13 Software
      1. 12.13.1 ADC Examples
        1. 12.13.1.1 ADC Software Triggering
        2. 12.13.1.2 ADC MCPWM Triggering
        3. 12.13.1.3 ADC Temperature Sensor Conversion
        4. 12.13.1.4 ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        5. 12.13.1.5 ADC PPB Offset (adc_ppb_offset)
        6. 12.13.1.6 ADC PPB Limits (adc_ppb_limits)
        7. 12.13.1.7 ADC SOC Oversampling
        8. 12.13.1.8 ADC Trigger Repeater Oversampling
    14. 12.14 ADC Registers
      1. 12.14.1 ADC Base Address Table
      2. 12.14.2 ADC_LITE_RESULT_REGS Registers
      3. 12.14.3 ADC_LITE_REGS Registers
  15. 13Comparator Subsystem (CMPSS)
    1. 13.1 Introduction
      1. 13.1.1 Features
      2. 13.1.2 CMPSS Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2 Comparator
    3. 13.3 Reference DAC
    4. 13.4 Digital Filter
      1. 13.4.1 Filter Initialization Sequence
    5. 13.5 Using the CMPSS
      1. 13.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 13.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 13.5.3 Calibrating the CMPSS
      4. 13.5.4 Enabling and Disabling the CMPSS Clock
    6. 13.6 CMPSS DAC Output
    7. 13.7 Software
      1. 13.7.1 CMPSS Examples
      2. 13.7.2 CMPSS_LITE Examples
        1. 13.7.2.1 CMPSSLITE Asynchronous Trip
    8. 13.8 CMPSS Registers
      1. 13.8.1 CMPSS Base Address Table
      2. 13.8.2 CMPSS_LITE_REGS Registers
  16. 14Programmable Gain Amplifier (PGA)
    1. 14.1  Programmable Gain Amplifier (PGA) Overview
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
    2. 14.2  Linear Output Range
    3. 14.3  Gain Values
    4. 14.4  Modes of Operation
      1. 14.4.1 Buffer Mode
      2. 14.4.2 Standalone Mode
      3. 14.4.3 Non-inverting Mode
      4. 14.4.4 Subtractor Mode
    5. 14.5  External Filtering
      1. 14.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 14.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 14.6  Error Calibration
      1. 14.6.1 Offset Error
      2. 14.6.2 Gain Error
    7. 14.7  Chopping Feature
    8. 14.8  Enabling and Disabling the PGA Clock
    9. 14.9  Lock Register
    10. 14.10 Analog Front-End Integration
      1. 14.10.1 Analog-to-Digital Converter (ADC)
        1. 14.10.1.1 Unfiltered Acquisition Window
        2. 14.10.1.2 Filtered Acquisition Window
      2. 14.10.2 Comparator Subsystem (CMPSS)
      3. 14.10.3 Alternate Functions
    11. 14.11 Examples
      1. 14.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 14.11.2 Buffer Mode
      3. 14.11.3 Low-Side Current Sensing
      4. 14.11.4 Bidirectional Current Sensing
    12. 14.12 Software
      1. 14.12.1 PGA Examples
        1. 14.12.1.1 PGA CMPSSDAC-ADC External Loopback Example
    13. 14.13 PGA Registers
      1. 14.13.1 PGA Base Address Table
      2. 14.13.2 PGA_REGS Registers
  17. 15Multi-Channel Pulse Width Modulator (MCPWM)
    1. 15.1  Introduction
      1. 15.1.1 PWM Related Collateral
      2. 15.1.2 Submodule Overview
    2. 15.2  Configuring Device Pins
    3. 15.3  MCPWM Modules Overview
    4. 15.4  Time-Base (TB) Submodule
      1. 15.4.1 Purpose of the Time-Base Submodule
      2. 15.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 15.4.3 Calculating PWM Period and Frequency
        1. 15.4.3.1 Time-Base Period Shadow Register
        2. 15.4.3.2 Time-Base Clock Synchronization
        3. 15.4.3.3 Time-Base Counter Synchronization
        4. 15.4.3.4 MCPWM SYNC Selection
      4. 15.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 15.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 15.4.6 Global Load
        1. 15.4.6.1 One-Shot Load Mode
    5. 15.5  Counter-Compare (CC) Submodule
      1. 15.5.1 Purpose of the Counter-Compare Submodule
      2. 15.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 15.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 15.5.4 Count Mode Timing Waveforms
    6. 15.6  Action-Qualifier (AQ) Submodule
      1. 15.6.1 Purpose of the Action-Qualifier Submodule
      2. 15.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 15.6.3 Action-Qualifier Event Priority
      4. 15.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 15.6.5 Configuration Requirements for Common Waveforms
    7. 15.7  Dead-Band Generator (DB) Submodule
      1. 15.7.1 Purpose of the Dead-Band Submodule
      2. 15.7.2 Dead-Band Submodule Additional Operating Modes
      3. 15.7.3 Operational Highlights for the Dead-Band Submodule
    8. 15.8  Trip-Zone (TZ) Submodule
      1. 15.8.1 Purpose of the Trip-Zone Submodule
      2. 15.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 15.8.2.1 Trip-Zone Configurations
      3. 15.8.3 Generating Trip Event Interrupts
    9. 15.9  Event-Trigger (ET) Submodule
      1. 15.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 15.10 PWM Crossbar (X-BAR)
    11. 15.11 Software
      1. 15.11.1 MCPWM Examples
        1. 15.11.1.1 MCPWM Basic PWM Generation and Updates
        2. 15.11.1.2 MCPWM Basic PWM Generation and Updates
        3. 15.11.1.3 MCPWM Basic PWM generation With DeadBand
        4. 15.11.1.4 MCPWM Basic PWM Generation and Updates without Sysconfig
        5. 15.11.1.5 MCPWM PWM Tripzone Feature Showcase
        6. 15.11.1.6 MCPWM Global Load Feature Showcase
        7. 15.11.1.7 MCPWM DMA Configuration for Dynamic PWM Control
    12. 15.12 MCPWM Registers
      1. 15.12.1 MCPWM Base Address Table
      2. 15.12.2 MCPWM_6CH_REGS Registers
      3. 15.12.3 MCPWM_2CH_REGS Registers
  18. 16Enhanced Capture (eCAP)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 ECAP Related Collateral
    2. 16.2 Description
    3. 16.3 Configuring Device Pins for the eCAP
    4. 16.4 Capture and APWM Operating Mode
    5. 16.5 Capture Mode Description
      1. 16.5.1 Event Prescaler
      2. 16.5.2 Edge Polarity Select and Qualifier
      3. 16.5.3 Continuous/One-Shot Control
      4. 16.5.4 32-Bit Counter and Phase Control
      5. 16.5.5 CAP1-CAP4 Registers
      6. 16.5.6 eCAP Synchronization
        1. 16.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 16.5.7 Interrupt Control
      8. 16.5.8 Shadow Load and Lockout Control
      9. 16.5.9 APWM Mode Operation
    6. 16.6 Application of the eCAP Module
      1. 16.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 16.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 16.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 16.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 16.7 Application of the APWM Mode
      1. 16.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 16.8 Software
      1. 16.8.1 ECAP Examples
        1. 16.8.1.1 eCAP APWM Example
        2. 16.8.1.2 eCAP Capture PWM Example
    9. 16.9 ECAP Registers
      1. 16.9.1 ECAP Base Address Table
      2. 16.9.2 ECAP_REGS Registers
  19. 17Enhanced Quadrature Encoder Pulse (eQEP)
    1. 17.1  Introduction
      1. 17.1.1 EQEP Related Collateral
    2. 17.2  Configuring Device Pins
    3. 17.3  Description
      1. 17.3.1 EQEP Inputs
      2. 17.3.2 Functional Description
      3. 17.3.3 eQEP Memory Map
    4. 17.4  Quadrature Decoder Unit (QDU)
      1. 17.4.1 Position Counter Input Modes
        1. 17.4.1.1 Quadrature Count Mode
        2. 17.4.1.2 Direction-Count Mode
        3. 17.4.1.3 Up-Count Mode
        4. 17.4.1.4 Down-Count Mode
      2. 17.4.2 eQEP Input Polarity Selection
      3. 17.4.3 Position-Compare Sync Output
    5. 17.5  Position Counter and Control Unit (PCCU)
      1. 17.5.1 Position Counter Operating Modes
        1. 17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 17.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 17.5.2 Position Counter Latch
        1. 17.5.2.1 Index Event Latch
        2. 17.5.2.2 Strobe Event Latch
      3. 17.5.3 Position Counter Initialization
      4. 17.5.4 eQEP Position-compare Unit
    6. 17.6  eQEP Edge Capture Unit
    7. 17.7  eQEP Watchdog
    8. 17.8  eQEP Unit Timer Base
    9. 17.9  QMA Module
      1. 17.9.1 Modes of Operation
        1. 17.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 17.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 17.9.2 Interrupt and Error Generation
    10. 17.10 eQEP Interrupt Structure
    11. 17.11 Software
      1. 17.11.1 EQEP Examples
        1. 17.11.1.1 Frequency Measurement Using eQEP
        2. 17.11.1.2 Position and Speed Measurement Using eQEP
        3. 17.11.1.3 Frequency Measurement Using eQEP via unit timeout interrupt
        4. 17.11.1.4 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 17.12 EQEP Registers
      1. 17.12.1 EQEP Base Address Table
      2. 17.12.2 EQEP_REGS Registers
  20. 18Universal Asynchronous Receiver/Transmitter (UART)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Functional Description
      1. 18.2.1 Transmit and Receive Logic
      2. 18.2.2 Baud-Rate Generation
      3. 18.2.3 Data Transmission
      4. 18.2.4 Serial IR (SIR)
      5. 18.2.5 9-Bit UART Mode
      6. 18.2.6 FIFO Operation
      7. 18.2.7 Interrupts
      8. 18.2.8 Loopback Operation
      9. 18.2.9 DMA Operation
        1. 18.2.9.1 Receiving Data Using UART with DMA
        2. 18.2.9.2 Transmitting Data Using UART with DMA
    3. 18.3 Initialization and Configuration
    4. 18.4 Software
      1. 18.4.1 UART Examples
        1. 18.4.1.1 UART Echoback
        2. 18.4.1.2 UART Loopback
        3. 18.4.1.3 UART Loopback with interrupt
        4. 18.4.1.4 UART Digital Loopback with DMA
    5. 18.5 UART Registers
      1. 18.5.1 UART Base Address Table
      2. 18.5.2 UART_REGS Registers
      3. 18.5.3 UART_REGS_WRITE Registers
  21. 19Serial Peripheral Interface (SPI)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 Block Diagram
    2. 19.2 System-Level Integration
      1. 19.2.1 SPI Module Signals
      2. 19.2.2 Configuring Device Pins
        1. 19.2.2.1 GPIOs Required for High-Speed Mode
      3. 19.2.3 SPI Interrupts
      4. 19.2.4 DMA Support
    3. 19.3 SPI Operation
      1. 19.3.1  Introduction to Operation
      2. 19.3.2  Controller Mode
      3. 19.3.3  Peripheral Mode
      4. 19.3.4  Data Format
        1. 19.3.4.1 Transmission of Bit from SPIRXBUF
      5. 19.3.5  Baud Rate Selection
        1. 19.3.5.1 Baud Rate Determination
        2. 19.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 19.3.6  SPI Clocking Schemes
      7. 19.3.7  SPI FIFO Description
      8. 19.3.8  SPI DMA Transfers
        1. 19.3.8.1 Transmitting Data Using SPI with DMA
        2. 19.3.8.2 Receiving Data Using SPI with DMA
      9. 19.3.9  SPI High-Speed Mode
      10. 19.3.10 SPI 3-Wire Mode Description
    4. 19.4 Programming Procedure
      1. 19.4.1 Initialization Upon Reset
      2. 19.4.2 Configuring the SPI
      3. 19.4.3 Configuring the SPI for High-Speed Mode
      4. 19.4.4 Data Transfer Example
      5. 19.4.5 SPI 3-Wire Mode Code Examples
        1. 19.4.5.1 3-Wire Controller Mode Transmit
        2.       679
          1. 19.4.5.2.1 3-Wire Controller Mode Receive
        3.       681
          1. 19.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       683
          1. 19.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 19.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 19.5 Software
      1. 19.5.1 SPI Examples
        1. 19.5.1.1 SPI Digital Loopback
        2. 19.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 19.5.1.3 SPI Digital Loopback with DMA
        4. 19.5.1.4 SPI EEPROM
        5. 19.5.1.5 SPI DMA EEPROM
    6. 19.6 SPI Registers
      1. 19.6.1 SPI Base Address Table
      2. 19.6.2 SPI_REGS Registers
  22. 20Inter-Integrated Circuit Module (I2C)
    1. 20.1 Introduction
      1. 20.1.1 I2C Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Features Not Supported
      4. 20.1.4 Functional Overview
      5. 20.1.5 Clock Generation
      6. 20.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 20.1.6.1 Formula for the Controller Clock Period
    2. 20.2 Configuring Device Pins
    3. 20.3 I2C Module Operational Details
      1. 20.3.1  Input and Output Voltage Levels
      2. 20.3.2  Selecting Pullup Resistors
      3. 20.3.3  Data Validity
      4. 20.3.4  Operating Modes
      5. 20.3.5  I2C Module START and STOP Conditions
      6. 20.3.6  Non-repeat Mode versus Repeat Mode
      7. 20.3.7  Serial Data Formats
        1. 20.3.7.1 7-Bit Addressing Format
        2. 20.3.7.2 10-Bit Addressing Format
        3. 20.3.7.3 Free Data Format
        4. 20.3.7.4 Using a Repeated START Condition
      8. 20.3.8  Clock Synchronization
      9. 20.3.9  Clock Stretching
      10. 20.3.10 Arbitration
      11. 20.3.11 Digital Loopback Mode
      12. 20.3.12 NACK Bit Generation
    4. 20.4 Interrupt Requests Generated by the I2C Module
      1. 20.4.1 Basic I2C Interrupt Requests
      2. 20.4.2 I2C FIFO Interrupts
    5. 20.5 Resetting or Disabling the I2C Module
    6. 20.6 Software
      1. 20.6.1 I2C Registers to Driverlib Functions
      2. 20.6.2 I2C Examples
        1. 20.6.2.1 C28x-I2C Library source file for FIFO interrupts
        2. 20.6.2.2 C28x-I2C Library source file for FIFO using polling
        3. 20.6.2.3 I2C Digital Loopback with FIFO Interrupts
        4. 20.6.2.4 I2C EEPROM
        5. 20.6.2.5 I2C EEPROM
        6. 20.6.2.6 I2C EEPROM
    7. 20.7 I2C Registers
      1. 20.7.1 I2C Base Address Table
      2. 20.7.2 I2C_REGS Registers
  23. 21Serial Communications Interface (SCI)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 SCI Related Collateral
      3. 21.1.3 Block Diagram
    2. 21.2  Architecture
    3. 21.3  SCI Module Signal Summary
    4. 21.4  Configuring Device Pins
    5. 21.5  Multiprocessor and Asynchronous Communication Modes
    6. 21.6  SCI Programmable Data Format
    7. 21.7  SCI Multiprocessor Communication
      1. 21.7.1 Recognizing the Address Byte
      2. 21.7.2 Controlling the SCI TX and RX Features
      3. 21.7.3 Receipt Sequence
    8. 21.8  Idle-Line Multiprocessor Mode
      1. 21.8.1 Idle-Line Mode Steps
      2. 21.8.2 Block Start Signal
      3. 21.8.3 Wake-Up Temporary (WUT) Flag
        1. 21.8.3.1 Sending a Block Start Signal
      4. 21.8.4 Receiver Operation
    9. 21.9  Address-Bit Multiprocessor Mode
      1. 21.9.1 Sending an Address
    10. 21.10 SCI Communication Format
      1. 21.10.1 Receiver Signals in Communication Modes
      2. 21.10.2 Transmitter Signals in Communication Modes
    11. 21.11 SCI Port Interrupts
      1. 21.11.1 Break Detect
    12. 21.12 SCI Baud Rate Calculations
    13. 21.13 SCI Enhanced Features
      1. 21.13.1 SCI FIFO Description
      2. 21.13.2 SCI Auto-Baud
      3. 21.13.3 Autobaud-Detect Sequence
    14. 21.14 Software
      1. 21.14.1 SCI Examples
        1. 21.14.1.1 Tune Baud Rate via UART Example
        2. 21.14.1.2 SCI FIFO Digital Loop Back
        3. 21.14.1.3 SCI Digital Loop Back with Interrupts
        4. 21.14.1.4 SCI Echoback
        5. 21.14.1.5 stdout redirect example
    15. 21.15 SCI Registers
      1. 21.15.1 SCI Base Address Table
      2. 21.15.2 SCI_REGS Registers
  24. 22Revision History

16.9.2 ECAP_REGS Registers

Table 16-3 lists the memory-mapped registers for the ECAP_REGS registers. All register offset addresses not listed in Table 16-3 should be considered as reserved locations and the register contents should not be modified.

Table 16-3 ECAP_REGS Registers
OffsetAcronymRegister NameWrite Protection
0hTSCTRTime-Stamp Counter
2hCTRPHSCounter Phase Offset Value Register
4hCAP1Capture 1 Register
6hCAP2Capture 2 Register
8hCAP3Capture 3 Register
AhCAP4Capture 4 Register
12hECCTL0Capture Control Register 0EALLOW
14hECCTL1Capture Control Register 1EALLOW
15hECCTL2Capture Control Register 2EALLOW
16hECEINTCapture Interrupt Enable RegisterEALLOW
17hECFLGCapture Interrupt Flag Register
18hECCLRCapture Interrupt Clear Register
19hECFRCCapture Interrupt Force RegisterEALLOW
1EhECAPSYNCINSELSYNC source select registerEALLOW

Complex bit access types are encoded to fit into small table cells. Table 16-4 shows the codes that are used for access types in this section.

Table 16-4 ECAP_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value

16.9.2.1 TSCTR Register (Offset = 0h) [Reset = 00000000h]

TSCTR is shown in Figure 16-17 and described in Table 16-5.

Return to the Summary Table.

Time-Stamp Counter

Figure 16-17 TSCTR Register
313029282726252423222120191817161514131211109876543210
TSCTR
R/W-0h
Table 16-5 TSCTR Register Field Descriptions
BitFieldTypeResetDescription
31-0TSCTRR/W0hActive 32-bit counter register that is used as the capture time-base
HR mode :
1) This register reads HRCOUNTER value and is not writable
2) can be reset using CTRFILTRESET
3) Its not synchronized to SYSCLK domain so reads may not be accurate

Reset type: SYSRSn

16.9.2.2 CTRPHS Register (Offset = 2h) [Reset = 00000000h]

CTRPHS is shown in Figure 16-18 and described in Table 16-6.

Return to the Summary Table.

Counter Phase Offset Value Register

Figure 16-18 CTRPHS Register
313029282726252423222120191817161514131211109876543210
CTRPHS
R/W-0h
Table 16-6 CTRPHS Register Field Descriptions
BitFieldTypeResetDescription
31-0CTRPHSR/W0hCounter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and PWM time-bases.
This register is not applicable in HR mode.

Reset type: SYSRSn

16.9.2.3 CAP1 Register (Offset = 4h) [Reset = 00000000h]

CAP1 is shown in Figure 16-19 and described in Table 16-7.

Return to the Summary Table.

Capture 1 Register

Figure 16-19 CAP1 Register
313029282726252423222120191817161514131211109876543210
CAP1
R/W-0h
Table 16-7 CAP1 Register Field Descriptions
BitFieldTypeResetDescription
31-0CAP1R/W0hThis register can be loaded (written) by:
- Time-Stamp counter value (TSCTR) during a capture event
- Software - may be useful for test purposes or initialization
- ARPD shadow register (CAP3) when used in APWM mode

Reset type: SYSRSn

16.9.2.4 CAP2 Register (Offset = 6h) [Reset = 00000000h]

CAP2 is shown in Figure 16-20 and described in Table 16-8.

Return to the Summary Table.

Capture 2 Register

Figure 16-20 CAP2 Register
313029282726252423222120191817161514131211109876543210
CAP2
R/W-0h
Table 16-8 CAP2 Register Field Descriptions
BitFieldTypeResetDescription
31-0CAP2R/W0hThis register can be loaded (written) by:
- Time-Stamp ( counter value) during a capture event
- Software - may be useful for test purposes
- ACMP shadow register (CAP4) when used in APWM mode

Reset type: SYSRSn

16.9.2.5 CAP3 Register (Offset = 8h) [Reset = 00000000h]

CAP3 is shown in Figure 16-21 and described in Table 16-9.

Return to the Summary Table.

Capture 3 Register

Figure 16-21 CAP3 Register
313029282726252423222120191817161514131211109876543210
CAP3
R/W-0h
Table 16-9 CAP3 Register Field Descriptions
BitFieldTypeResetDescription
31-0CAP3R/W0hIn CMP mode, this is a time-stamp capture register.

In APWM mode, this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode.

Reset type: SYSRSn

16.9.2.6 CAP4 Register (Offset = Ah) [Reset = 00000000h]

CAP4 is shown in Figure 16-22 and described in Table 16-10.

Return to the Summary Table.

Capture 4 Register

Figure 16-22 CAP4 Register
313029282726252423222120191817161514131211109876543210
CAP4
R/W-0h
Table 16-10 CAP4 Register Field Descriptions
BitFieldTypeResetDescription
31-0CAP4R/W0hIn CMP mode, this is a time-stamp capture register.

In APWM mode, this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode.

Reset type: SYSRSn

16.9.2.7 ECCTL0 Register (Offset = 12h) [Reset = 0000007Fh]

ECCTL0 is shown in Figure 16-23 and described in Table 16-11.

Return to the Summary Table.

Capture Control Register 0

Figure 16-23 ECCTL0 Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDINPUTSEL
R-0-0hR/W-7Fh
Table 16-11 ECCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR-00hReserved
6-0INPUTSELR/W7FhCapture input source select bits
0000000 capture input is ECAPxINPUT[0]
0000001 capture input is ECAPxINPUT[1]
0000010 capture input is ECAPxINPUT[2]
...
1111111 capture input is ECAPxINPUT[127]

Reset type: CPU1.SYSRSn

16.9.2.8 ECCTL1 Register (Offset = 14h) [Reset = 0000h]

ECCTL1 is shown in Figure 16-24 and described in Table 16-12.

Return to the Summary Table.

Capture Control Register 1

Figure 16-24 ECCTL1 Register
15141312111098
FREE_SOFTPRESCALECAPLDEN
R/W-0hR/W-0hR/W-0h
76543210
CTRRST4CAP4POLCTRRST3CAP3POLCTRRST2CAP2POLCTRRST1CAP1POL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 16-12 ECCTL1 Register Field Descriptions
BitFieldTypeResetDescription
15-14FREE_SOFTR/W0hEmulation Control

Reset type: SYSRSn


0h (R/W) = TSCTR counter stops immediately on emulation suspend
1h (R/W) = TSCTR counter runs until = 0
2h (R/W) = TSCTR counter is unaffected by emulation suspend (Run Free)
3h (R/W) = TSCTR counter is unaffected by emulation suspend (Run Free)
13-9PRESCALER/W0hEvent Filter prescale select

Reset type: SYSRSn


0h (R/W) = Divide by 1 (i.e,. no prescale, by-pass the prescaler)
1h (R/W) = Divide by 2
2h (R/W) = Divide by 4
3h (R/W) = Divide by 6
4h (R/W) = Divide by 8
5h (R/W) = Divide by 10
1Eh (R/W) = Divide by 60
1Fh (R/W) = Divide by 62
8CAPLDENR/W0hEnable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated.

Reset type: SYSRSn


0h (R/W) = Disable CAP1-4 register loads at capture event time.
1h (R/W) = Enable CAP1-4 register loads at capture event time.
7CTRRST4R/W0hCounter Reset on Capture Event 4

Reset type: SYSRSn


0h (R/W) = Do not reset counter on Capture Event 4 (absolute time stamp operation)
1h (R/W) = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)
6CAP4POLR/W0hCapture Event 4 Polarity select

Reset type: SYSRSn


0h (R/W) = Capture Event 4 triggered on a rising edge (RE)
1h (R/W) = Capture Event 4 triggered on a falling edge (FE)
5CTRRST3R/W0hCounter Reset on Capture Event 3

Reset type: SYSRSn


0h (R/W) = Do not reset counter on Capture Event 3 (absolute time stamp)
1h (R/W) = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)
4CAP3POLR/W0hCapture Event 3 Polarity select

Reset type: SYSRSn


0h (R/W) = Capture Event 3 triggered on a rising edge (RE)
1h (R/W) = Capture Event 3 triggered on a falling edge (FE)
3CTRRST2R/W0hCounter Reset on Capture Event 2

Reset type: SYSRSn


0h (R/W) = Do not reset counter on Capture Event 2 (absolute time stamp)
1h (R/W) = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)
2CAP2POLR/W0hCapture Event 2 Polarity select

Reset type: SYSRSn


0h (R/W) = Capture Event 2 triggered on a rising edge (RE)
1h (R/W) = Capture Event 2 triggered on a falling edge (FE)
1CTRRST1R/W0hCounter Reset on Capture Event 1

Reset type: SYSRSn


0h (R/W) = Do not reset counter on Capture Event 1 (absolute time stamp)
1h (R/W) = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)
0CAP1POLR/W0hCapture Event 1 Polarity select

Reset type: SYSRSn


0h (R/W) = Capture Event 1 triggered on a rising edge (RE)
1h (R/W) = Capture Event 1 triggered on a falling edge (FE)

16.9.2.9 ECCTL2 Register (Offset = 15h) [Reset = 0006h]

ECCTL2 is shown in Figure 16-25 and described in Table 16-13.

Return to the Summary Table.

Capture Control Register 2

Figure 16-25 ECCTL2 Register
15141312111098
MODCNTRSTSDMAEVTSELCTRFILTRESETAPWMPOLCAP_APWMSWSYNC
R-0hR/W-0hR-0/W1C-0hR/W-0hR/W-0hR-0/W1S-0h
76543210
SYNCO_SELSYNCI_ENTSCTRSTOPREARMSTOP_WRAPCONT_ONESHT
R/W-0hR/W-0hR/W-0hR-0/W1S-0hR/W-3hR/W-0h
Table 16-13 ECCTL2 Register Field Descriptions
BitFieldTypeResetDescription
15-14MODCNTRSTSR0hThis bit field reads current status on modulo counter
00b (R) = CAP1 register gets loaded on next capture event.
01b (R) = CAP2 register gets loaded on next capture event.
10b (R) = CAP3 register gets loaded on next capture event.
11b (R) = CAP4 register gets loaded on next capture event.

Reset type: CPU1.SYSRSn

13-12DMAEVTSELR/W0hDMA event select
00b (R/W) = DMA interrupt source is CEVT1
01b (R/W) = DMA interrupt source is CEVT2
10b (R/W) = DMA interrupt source is CEVT3
11b (R/W) = DMA interrupt source is CEVT4

Note: ECCTL1.CAPLDEN also needs to be set to '1' for ECAPxDMA_INT to be generated

Reset type: CPU1.SYSRSn

11CTRFILTRESETR-0/W1C0hReset Bit
0h (R) = No effect
1h (W) = Resets event filter, counter, modulo counter and CEVT[1,2,3,4] and CNTOVF , HRERROR flags

Note: This provides an ability start capture module from known state in case spurious inputs are captured while ECAP is configured.

Reset type: CPU1.SYSRSn

10APWMPOLR/W0hAPWM output polarity select. This is applicable only in APWM operating mode.

Reset type: SYSRSn


0h (R/W) = Output is active high (Compare value defines high time)
1h (R/W) = Output is active low (Compare value defines low time)
9CAP_APWMR/W0hCAP/APWM operating mode select

Reset type: SYSRSn


0h (R/W) = ECAP module operates in capture mode. This mode forces the following configuration:
- Inhibits TSCTR resets via CTR = PRD event
- Inhibits shadow loads on CAP1 and 2 registers
- Permits user to enable CAP1-4 register load
- CAPx/APWMx pin operates as a capture input
1h (R/W) = ECAP module operates in APWM mode. This mode forces the following configuration:
- Resets TSCTR on CTR = PRD event (period boundary
- Permits shadow loading on CAP1 and 2 registers
- Disables loading of time-stamps into CAP1-4 registers
- CAPx/APWMx pin operates as a APWM output
8SWSYNCR-0/W1S0hSoftware-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode, the synchronization pulse can also be sourced from the CTR = PRD event.

Reset type: SYSRSn


0h (R/W) = Writing a zero has no effect. Reading always returns a zero
1h (R/W) = Writing a one forces a TSCTR shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 0,0. After writing a 1, this bit returns to a zero.
7-6SYNCO_SELR/W0hSync-Out Select

Reset type: SYSRSn


0h (R/W) = sync out signal is SWSYNC
1h (R/W) = Select CTR = PRD event to be the sync-out signal. Note: Selection CTR = PRD is meaningful only in APWM mode
2h (R/W) = Disable sync out signal
3h (R/W) = Disable sync out signal
5SYNCI_ENR/W0hCounter (TSCTR) Sync-In select mode

Reset type: SYSRSn


0h (R/W) = Disable sync-in option
1h (R/W) = Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event.
4TSCTRSTOPR/W0hTime Stamp (TSCTR) Counter Stop (freeze) Control

Reset type: SYSRSn


0h (R/W) = TSCTR stopped
1h (R/W) = TSCTR free-running
3REARMR-0/W1S0hRe-Arming Control. Note: The re-arm function is valid in one shot or continuous mode

Reset type: SYSRSn


0h (R/W) = Has no effect (reading always returns a 0)
1h (R/W) = Arms the one-shot sequence as follows:
1) Resets the Mod4 counter to zero
2) Unfreezes the Mod4 counter
3) Enables capture register loads
2-1STOP_WRAPR/W3hStop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen, that is, capture sequence is stopped.
Wrap value for continuous mode. This is the number (between 1-4) of the capture register in which the circular buffer wraps around and starts again.
Notes: STOP_WRAP is compared to Mod4 counter and, when equal, 2 actions occur:
- Mod4 counter is stopped (frozen)
- Capture register loads are inhibited
In one-shot mode, further interrupt events are blocked until re-armed.

Reset type: SYSRSn


0h (R/W) = Stop after Capture Event 1 in one-shot mode
Wrap after Capture Event 1 in continuous mode.
1h (R/W) = Stop after Capture Event 2 in one-shot mode
Wrap after Capture Event 2 in continuous mode.
2h (R/W) = Stop after Capture Event 3 in one-shot mode
Wrap after Capture Event 3 in continuous mode.
3h (R/W) = Stop after Capture Event 4 in one-shot mode
Wrap after Capture Event 4 in continuous mode.
0CONT_ONESHTR/W0hContinuous or one-shot mode control (applicable only in capture mode)

Reset type: SYSRSn


0h (R/W) = Operate in continuous mode
1h (R/W) = Operate in one-Shot mode

16.9.2.10 ECEINT Register (Offset = 16h) [Reset = 0000h]

ECEINT is shown in Figure 16-26 and described in Table 16-14.

Return to the Summary Table.

The interrupt enable bits (CEVT1, ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers.

The proper procedure for configuring peripheral modes and interrupts is as follows:

- Disable global interrupts
- Stop eCAP counter
- Disable eCAP interrupts
- Configure peripheral registers
- Clear spurious eCAP interrupt flags
- Enable eCAP interrupts
- Start eCAP counter
- Enable global interrupts

Figure 16-26 ECEINT Register
15141312111098
RESERVEDRESERVED
R-0hR/W-0h
76543210
CTR_EQ_CMPCTR_EQ_PRDCTROVFCEVT4CEVT3CEVT2CEVT1RESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 16-14 ECEINT Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0hReserved
8RESERVEDR/W0hReserved
7CTR_EQ_CMPR/W0hCounter Equal Compare Interrupt Enable

Reset type: SYSRSn


0h (R/W) = Disable Compare Equal as an Interrupt source
1h (R/W) = Enable Compare Equal as an Interrupt source
6CTR_EQ_PRDR/W0hCounter Equal Period Interrupt Enable

Reset type: SYSRSn


0h (R/W) = Disable Period Equal as an Interrupt source
1h (R/W) = Enable Period Equal as an Interrupt source
5CTROVFR/W0hCounter Overflow Interrupt Enable

Reset type: SYSRSn


0h (R/W) = Disabled counter Overflow as an Interrupt source
1h (R/W) = Enable counter Overflow as an Interrupt source
4CEVT4R/W0hCapture Event 4 Interrupt Enable

Reset type: SYSRSn


0h (R/W) = Disable Capture Event 4 as an Interrupt source
1h (R/W) = Capture Event 4 Interrupt Enable
3CEVT3R/W0hCapture Event 3 Interrupt Enable

Reset type: SYSRSn


0h (R/W) = Disable Capture Event 3 as an Interrupt source
1h (R/W) = Enable Capture Event 3 as an Interrupt source
2CEVT2R/W0hCapture Event 2 Interrupt Enable

Reset type: SYSRSn


0h (R/W) = Disable Capture Event 2 as an Interrupt source
1h (R/W) = Enable Capture Event 2 as an Interrupt source
1CEVT1R/W0hCapture Event 1 Interrupt Enable

Reset type: SYSRSn


0h (R/W) = Disable Capture Event 1 as an Interrupt source
1h (R/W) = Enable Capture Event 1 as an Interrupt source
0RESERVEDR0hReserved

16.9.2.11 ECFLG Register (Offset = 17h) [Reset = 0000h]

ECFLG is shown in Figure 16-27 and described in Table 16-15.

Return to the Summary Table.

Capture Interrupt Flag Register

Figure 16-27 ECFLG Register
15141312111098
RESERVEDRESERVED
R-0hR-0h
76543210
CTR_CMPCTR_PRDCTROVFCEVT4CEVT3CEVT2CEVT1INT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 16-15 ECFLG Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0hReserved
8RESERVEDR0hReserved
7CTR_CMPR0hCompare Equal Compare Status Flag. This flag is active only in APWM mode.

Reset type: SYSRSn


0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) reached the compare register value (ACMP)
6CTR_PRDR0hCounter Equal Period Status Flag. This flag is only active in APWM mode.

Reset type: SYSRSn


0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) reached the period register value (APRD) and was reset.
5CTROVFR0hCounter Overflow Status Flag. This flag is active in CAP and APWM mode.

Reset type: SYSRSn


0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000
4CEVT4R0hCapture Event 4 Status Flag This flag is only active in CAP mode.

Reset type: SYSRSn


0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the fourth event occurred at ECAPx pin
3CEVT3R0hCapture Event 3 Status Flag. This flag is active only in CAP mode.

Reset type: SYSRSn


0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the third event occurred at ECAPx pin.
2CEVT2R0hCapture Event 2 Status Flag. This flag is only active in CAP mode.

Reset type: SYSRSn


0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the second event occurred at ECAPx pin.
1CEVT1R0hCapture Event 1 Status Flag. This flag is only active in CAP mode.

Reset type: SYSRSn


0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the first event occurred at ECAPx pin.
0INTR0hGlobal Interrupt Status Flag

Reset type: SYSRSn


0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates that an interrupt was generated.

16.9.2.12 ECCLR Register (Offset = 18h) [Reset = 0000h]

ECCLR is shown in Figure 16-28 and described in Table 16-16.

Return to the Summary Table.

Capture Interrupt Clear Register

Figure 16-28 ECCLR Register
15141312111098
RESERVEDRESERVED
R-0hR-0/W1C-0h
76543210
CTR_CMPCTR_PRDCTROVFCEVT4CEVT3CEVT2CEVT1INT
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 16-16 ECCLR Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0hReserved
8RESERVEDR-0/W1C0hReserved
7CTR_CMPR-0/W1C0hCounter Equal Compare Status Clear

Reset type: SYSRSn


0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTR=CMP flag.
6CTR_PRDR-0/W1C0hCounter Equal Period Status Clear

Reset type: SYSRSn


0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTR=PRD flag.
5CTROVFR-0/W1C0hCounter Overflow Status Clear

Reset type: SYSRSn


0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTROVF flag.
4CEVT4R-0/W1C0hCapture Event 4 Status Clear

Reset type: SYSRSn


0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT4 flag.
3CEVT3R-0/W1C0hCapture Event 3 Status Clear

Reset type: SYSRSn


0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT3 flag.
2CEVT2R-0/W1C0hCapture Event 2 Status Clear

Reset type: SYSRSn


0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT2 flag.
1CEVT1R-0/W1C0hCapture Event 1 Status Clear

Reset type: SYSRSn


0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT1 flag.
0INTR-0/W1C0hECAP Global Interrupt Status Clear

Reset type: SYSRSn


0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1

16.9.2.13 ECFRC Register (Offset = 19h) [Reset = 0000h]

ECFRC is shown in Figure 16-29 and described in Table 16-17.

Return to the Summary Table.

Capture Interrupt Force Register

Figure 16-29 ECFRC Register
15141312111098
RESERVEDRESERVED
R-0hR-0/W1S-0h
76543210
CTR_CMPCTR_PRDCTROVFCEVT4CEVT3CEVT2CEVT1RESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0h
Table 16-17 ECFRC Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0hReserved
8RESERVEDR-0/W1S0hReserved
7CTR_CMPR-0/W1S0hForce Counter Equal Compare Interrupt. This event is only active in APWM mode.

Reset type: SYSRSn


0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CTR_CMP flag.
6CTR_PRDR-0/W1S0hForce Counter Equal Period Interrupt. This event is only active in APWM mode.

Reset type: SYSRSn


0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CTR_PRD flag.
5CTROVFR-0/W1S0hForce Counter Overflow

Reset type: SYSRSn


0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 to this bit sets the CTROVF flag.
4CEVT4R-0/W1S0hForce Capture Event 4. This event is only active in CAP mode.

Reset type: SYSRSn


0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT4 flag.
3CEVT3R-0/W1S0hForce Capture Event 3. This event is only active in CAP mode.

Reset type: SYSRSn


0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT3 flag.
2CEVT2R-0/W1S0hForce Capture Event 2. This event is only active in CAP mode.

Reset type: SYSRSn


0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT2 flag.
1CEVT1R-0/W1S0hForce Capture Event 1. This event is only active in CAP mode.

Reset type: SYSRSn


0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Sets the CEVT1 flag.
0RESERVEDR0hReserved

16.9.2.14 ECAPSYNCINSEL Register (Offset = 1Eh) [Reset = 00000001h]

ECAPSYNCINSEL is shown in Figure 16-30 and described in Table 16-18.

Return to the Summary Table.

SYNC source select register

Figure 16-30 ECAPSYNCINSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL
R-0hR/W-1h
Table 16-18 ECAPSYNCINSEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-0SELR/W1hThese bits determines the source of SYNCIN signal.
0x0 : Disabled using SOC tieoff.
0x1-0x7F : Refer to MCPWM SYNCIN sources in MCPWM TRM chapter.

Reset type: SYSRSn