SPRUJ51 june   2023

 

  1.   1
  2. 1Abstract
  3. 2EVM Revisions and Assembly Variants
    1. 2.1 Inside the Box
    2. 2.2 EMC, EMI and ESD Compliance
  4.   Trademarks
  5. 3System Description
    1. 3.1 Key Features
      1. 3.1.1 Processor
      2. 3.1.2 Power Supply
      3. 3.1.3 Memory
      4. 3.1.4 JTAG Emulator
      5. 3.1.5 Supported Interfaces and Peripherals
      6. 3.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 3.2 Functional Block Diagram
    3. 3.3 AM62x-Low Power SK EVM Interface Mapping
    4. 3.4 Power ON OFF Procedures
      1. 3.4.1 Power-On Procedure
      2. 3.4.2 Power-Off Procedure
      3. 3.4.3 Power Test Points
    5. 3.5 Peripheral and Major Component Description
      1. 3.5.1  Clocking
      2. 3.5.2  Reset
      3. 3.5.3  OLDI Display Interface
      4. 3.5.4  CSI Interface
      5. 3.5.5  Audio Codec Interface
      6. 3.5.6  HDMI Display Interface
      7. 3.5.7  JTAG Interface
      8. 3.5.8  Test Automation Header
      9. 3.5.9  UART Interface
      10. 3.5.10 USB Interface
        1. 3.5.10.1 USB 2.0 Type A Interface
        2. 3.5.10.2 USB 2.0 Type C Interface
      11. 3.5.11 Memory Interfaces
        1. 3.5.11.1 LPDDR4 Interface
        2. 3.5.11.2 OSPI Interface
        3. 3.5.11.3 MMC Interfaces
          1. 3.5.11.3.1 MMC0 - eMMC Interface
          2. 3.5.11.3.2 MMC1 - Micro SD Interface
          3. 3.5.11.3.3 MMC2 - M2 Key E Interface
        4. 3.5.11.4 EEPROM
      12. 3.5.12 Ethernet Interface
        1. 3.5.12.1 CPSW Ethernet PHY1 Default Configuration
        2. 3.5.12.2 CPSW Ethernet PHY2 Default Configuration
      13. 3.5.13 GPIO Port Expander
      14. 3.5.14 GPIO Mapping
      15. 3.5.15 Power
        1. 3.5.15.1 Power Requirements
        2. 3.5.15.2 Power Input
        3. 3.5.15.3 Power Supply
        4. 3.5.15.4 Power Sequencing
        5. 3.5.15.5 AM62x 17x17 SoC Power
        6. 3.5.15.6 Current Monitoring
      16. 3.5.16 AM62x-Low Power SK EVM User Setup and Configuration
        1. 3.5.16.1 EVM DIP Switches
        2. 3.5.16.2 Boot Modes
        3. 3.5.16.3 User Test LEDs
      17. 3.5.17 Expansion Headers
        1. 3.5.17.1 User Expansion Connector
        2. 3.5.17.2 MCU Connector
        3. 3.5.17.3 PRU Connector
      18. 3.5.18 Push Buttons
      19. 3.5.19 I2C Address Mapping
  6. 4Known Issues and Modifications
  7. 5Revision History
  8. 6IMPORTANT NOTICE AND DISCLAIMER

3.5.3 OLDI Display Interface

The OLDI0 Display interface of the AM62x 17x17 SoC is connected to 40 pin LVDS display connector (J22) Mfr Part # FFC2A32-40-T from GCT. The OLDI Interface supports dual channel 8 bit LVDS output. The Pin-out details of the Display connector/ are given in the table below.

GUID-20230519-SS0I-DLRL-MRJC-357BHNXZGS4T-low.png Figure 3-9 OLDI Interface Block Diagram
Table 3-4 Display Connector Pinout
Pin no. Signal Pin no. Signal
1 VCC_3V3_SYS(EEPROM_VDD) 21 CH1_LVDS_A2P
2 SoC_I2C0_SCL 22 GND
3 SoC_I2C0_SDA 23 CH1_LVDS_A3N
4 NC 24 CH1_LVDS_A3P
5 NC 25 GND
6 GND 26 CH2_LVDS_A0N
7 GND 27 CH2_LVDS_A0P
8 OLDI_RESETn 28 GND
9 GPIO_OLDI_INT 29 CH2_LVDS_A1N
10 GND 30 CH2_LVDS_A1P
11 CH1_LVDS_A0N 31 GND
12 CH1_LVDS_A0P 32 CH2_LVDS_CLKN
13 GND 33 CH2_LVDS_CLKP
14 CH1_LVDS_A1N 34 GND
15 CH1_LVDS_A1P 35 CH2_LVDS_A2N
16 GND 36 CH2_LVDS_A2P
17 CH1_LVDS_CLKN 37 GND
18 CH1_LVDS_CLKP 38 CH2_LVDS_A3N
19 GND 39 CH2_LVDS_A3P
20 CH1_LVDS_A2N 40 GND