SPRUJ51 june   2023

 

  1.   1
  2. 1Abstract
  3. 2EVM Revisions and Assembly Variants
    1. 2.1 Inside the Box
    2. 2.2 EMC, EMI and ESD Compliance
  4.   Trademarks
  5. 3System Description
    1. 3.1 Key Features
      1. 3.1.1 Processor
      2. 3.1.2 Power Supply
      3. 3.1.3 Memory
      4. 3.1.4 JTAG Emulator
      5. 3.1.5 Supported Interfaces and Peripherals
      6. 3.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 3.2 Functional Block Diagram
    3. 3.3 AM62x-Low Power SK EVM Interface Mapping
    4. 3.4 Power ON OFF Procedures
      1. 3.4.1 Power-On Procedure
      2. 3.4.2 Power-Off Procedure
      3. 3.4.3 Power Test Points
    5. 3.5 Peripheral and Major Component Description
      1. 3.5.1  Clocking
      2. 3.5.2  Reset
      3. 3.5.3  OLDI Display Interface
      4. 3.5.4  CSI Interface
      5. 3.5.5  Audio Codec Interface
      6. 3.5.6  HDMI Display Interface
      7. 3.5.7  JTAG Interface
      8. 3.5.8  Test Automation Header
      9. 3.5.9  UART Interface
      10. 3.5.10 USB Interface
        1. 3.5.10.1 USB 2.0 Type A Interface
        2. 3.5.10.2 USB 2.0 Type C Interface
      11. 3.5.11 Memory Interfaces
        1. 3.5.11.1 LPDDR4 Interface
        2. 3.5.11.2 OSPI Interface
        3. 3.5.11.3 MMC Interfaces
          1. 3.5.11.3.1 MMC0 - eMMC Interface
          2. 3.5.11.3.2 MMC1 - Micro SD Interface
          3. 3.5.11.3.3 MMC2 - M2 Key E Interface
        4. 3.5.11.4 EEPROM
      12. 3.5.12 Ethernet Interface
        1. 3.5.12.1 CPSW Ethernet PHY1 Default Configuration
        2. 3.5.12.2 CPSW Ethernet PHY2 Default Configuration
      13. 3.5.13 GPIO Port Expander
      14. 3.5.14 GPIO Mapping
      15. 3.5.15 Power
        1. 3.5.15.1 Power Requirements
        2. 3.5.15.2 Power Input
        3. 3.5.15.3 Power Supply
        4. 3.5.15.4 Power Sequencing
        5. 3.5.15.5 AM62x 17x17 SoC Power
        6. 3.5.15.6 Current Monitoring
      16. 3.5.16 AM62x-Low Power SK EVM User Setup and Configuration
        1. 3.5.16.1 EVM DIP Switches
        2. 3.5.16.2 Boot Modes
        3. 3.5.16.3 User Test LEDs
      17. 3.5.17 Expansion Headers
        1. 3.5.17.1 User Expansion Connector
        2. 3.5.17.2 MCU Connector
        3. 3.5.17.3 PRU Connector
      18. 3.5.18 Push Buttons
      19. 3.5.19 I2C Address Mapping
  6. 4Known Issues and Modifications
  7. 5Revision History
  8. 6IMPORTANT NOTICE AND DISCLAIMER

3.5.5 Audio Codec Interface

AM62x-Low Power SK EVM uses TI‘s Low-Power TLV320AIC3106 Stereo Audio Codec to interface with AM62x via McASP. TLV320AIC3106 is a low-power stereo audio codec with stereo headphone amplifier, as well as multiple inputs and outputs programmable in single ended or fully differential configurations. The record path of the TLV320AIC3106 contains integrated microphone bias, digitally controlled stereo microphone preamplifier and Automatic gain control (AGC) with mix/Mux capability among the multiple analog inputs. The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz. 1x Standard 3.5mm TRRS Audio Jack connector Mfr. Part# SJ-43514 shall be provided for MIC and Headphone output. Audio Codec’s Line inputs are terminated to Test points. SELECT pin shall be held LOW to select I2C as control interface. Codec can be configured over I2C interface, where I2C address can be set by driving pins MFP0 and MFP1 pin either high or low. Both these pins are set to high, so the Device address is set to 0x1B. Unused inputs and outputs of the Audio Codec are connected to ground. The Controller Clock input, MCLK to the Audio Codec is provided through a 12.288MHz Oscillator. Audio serial data bus bit clock BCLK of the codec is driven by the AM62x SoC through a buffer. Audio serial data bus input and output DIN, DOUT are connected to SoC’s MCASP1_AXR0 and MCASP1_AXR2 through buffers. An AND output of RESETSTATz and a GPIO sourced via IO expander are used to reset the Audio codec. The TLV320AIC3106 is powered by an analog supply of 3.3 V, a digital core supply of 1.8 V, and a digital I/O supply 3.3 V.
GUID-20221024-SS0I-KLDD-ZMHD-KFSXQPNJG5T3-low.png Figure 3-11 Audio Codec Interface Block Diagram