SPRUJ51A June   2023  – November 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
  6. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Memory
      3. 2.2.3 JTAG Emulator
      4. 2.2.4 Supported Interfaces and Peripherals
      5. 2.2.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    3. 2.3  Power
      1. 2.3.1 Power Requirements
      2. 2.3.2 Power Input
      3. 2.3.3 Power Supply
      4. 2.3.4 Power ON OFF Procedures
        1. 2.3.4.1 Power-On Procedure
        2. 2.3.4.2 Power-Off Procedure
        3. 2.3.4.3 Power Test Points
      5. 2.3.5 Power Sequencing
      6. 2.3.6 AM62x 17x17 SoC Power
      7. 2.3.7 Current Monitoring
    4. 2.4  AM62x-Low Power SK EVM Interface Mapping
    5. 2.5  Clocking
    6. 2.6  Reset
    7. 2.7  OLDI Display Interface
    8. 2.8  CSI Interface
    9. 2.9  Audio Codec Interface
    10. 2.10 HDMI Display Interface
    11. 2.11 JTAG Interface
    12. 2.12 Test Automation Header
    13. 2.13 UART Interface
    14. 2.14 USB Interface
      1. 2.14.1 USB2.0 Type A Interface
      2. 2.14.2 USB2.0 Type C Interface
    15. 2.15 Memory Interfaces
      1. 2.15.1 LPDDR4 Interface
      2. 2.15.2 OSPI
      3. 2.15.3 MMC Interfaces
        1. 2.15.3.1 MMC0 - eMMC Interface
        2. 2.15.3.2 MMC1 - Micro SD Interface
        3. 2.15.3.3 MMC2 - M2 Key E Interface
      4. 2.15.4 EEPROM
    16. 2.16 Ethernet Interface
      1. 2.16.1 CPSW Ethernet PHY1 Default Configuration
      2. 2.16.2 CPSW Ethernet PHY2 Default Configuration
    17. 2.17 GPIO Port Expander
    18. 2.18 GPIO Mapping
    19. 2.19 AM62x-Low Power SK EVM User Setup and Configuration
      1. 2.19.1 EVM DIP Switches
      2. 2.19.2 Boot Modes
      3. 2.19.3 User Test LEDs
    20. 2.20 Expansion Headers
      1. 2.20.1 User Expansion Connector
      2. 2.20.2 MCU Connector
      3. 2.20.3 PRU Connector
    21. 2.21 Push Buttons
    22. 2.22 I2C Address Mapping
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 EMC, EMI and ESD Compliance
  9. 5Additional Information
    1. 5.1 Known Issues and Modifications
    2.     Trademarks
    3.     72
  10. 6Revision History

2.3.6 AM62x 17x17 SoC Power

The core voltage of the AM62x 17x17 SoC can be 0.75V or 0.85V based on the PMIC configuration and on the power optimization requirement. By default, the PMIC, configured as VDD_CORE = 0.75V, can be changed to 0.85V by changing the PMIC configuration register. Current monitors are provided on all the SoC power rails.

The SoC has different IO groups. Each IO group is powered by specific power supplies as shown in the table below.

Table 2-4 SoC Power Rails
Sl. No Power Supply SoC Supply Rails IO Power Group Voltage
1 VDD_CORE VDDA_CORE_USB 0.75
VDDA_CORE_CSI
VDD_CANUART CANUART
VDD_CORE CORE
2 VDDR_CORE VDDR_CORE CORE 0.85
3 VDDA_1V8 VDDA_1V8_CSIRX. CSI 1.8
VDDA_1V8_USB USB
VDDA_1V8_MCU
VDDA_1V8_OLDI OLDI
VDDA_1V8_OSCO OSCO
VDDA_PLL0, VDDA_PLL1,VDDA_PLL2
4 VDD_LPDDR4 VDDS_DDR DDR0 1.1
VDDS_DDR_C
5 VPP_1V8 VPP_1V8 1.8
6 SoC_VDDSHV5_SDIO VDDSHV5 MMC1 3.3
7 SOC_DVDD1V8 VDDSHV0 General 3.3
VDDSHV1 OSPI 1.8
VDDSHV4 MMC0
VDDSHV6 MMC2
VMON_1P8_SOC
8 SOC_DVDD3V3 VDDSHV0 General 3.3
VDDSHV2 RGMII
VDDSHV3 GPMC
VDDSHV_MCU MCU General
VMON_3P3_SOC
VDDA_3P3_USB USB