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  • KeyStone Architecture Multicore Navigator

    • SPRUGR9H November   2010  – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

       

  • CONTENTS
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  • KeyStone Architecture Multicore Navigator
  1.   Preface
    1.     About This Manual
    2.     Trademarks
    3.     Notational Conventions
    4.     Related Documentation from Texas Instruments
  2. 1Introduction
    1. 1.1  Terminology Used in This Document
    2. 1.2  KeyStone I Features
    3. 1.3  KeyStone I Functional Block Diagram
    4. 1.4  KeyStone II Changes to QMSS
    5. 1.5  KeyStone II QMSS Modes of Use
      1. 1.5.1 Shared Mode
      2. 1.5.2 Split Mode
    6. 1.6  Overview
    7. 1.7  Queue Manager
    8. 1.8  Packet DMA (PKTDMA)
    9. 1.9  Navigator Cloud
    10. 1.10 Virtualization
    11. 1.11 ARM-DSP Shared Use
    12. 1.12 PDSP Firmware
  3. 2Operational Concepts
    1. 2.1 Packets
    2. 2.2 Queues
      1. 2.2.1 Packet Queuing
      2. 2.2.2 Packet De-queuing
      3. 2.2.3 Queue Proxy
    3. 2.3 Queue Types
      1. 2.3.1 Transmit Queues
      2. 2.3.2 Transmit Completion Queues
      3. 2.3.3 Receive Queues
      4. 2.3.4 Free Descriptor Queues (FDQ)
        1. 2.3.4.1 Host Packet Free Descriptors
        2. 2.3.4.2 Monolithic Free Descriptors
      5. 2.3.5 Queue Pend Queues
    4. 2.4 Descriptors
      1. 2.4.1 Host Packet
      2. 2.4.2 Host Buffer
      3. 2.4.3 Monolithic Packet
    5. 2.5 Packet DMA
      1. 2.5.1 Channels
      2. 2.5.2 RX Flows
    6. 2.6 Packet Transmission Overview
    7. 2.7 Packet Reception Overview
    8. 2.8 ARM Endianess
  4. 3Descriptor Layouts
    1. 3.1 Host Packet Descriptor
    2. 3.2 Host Buffer Descriptor
    3. 3.3 Monolithic Descriptor
  5. 4Registers
    1. 4.1 Queue Manager
      1. 4.1.1 Queue Configuration Region
        1. 4.1.1.1 Revision Register (0x00000000)
        2. 4.1.1.2 Queue Diversion Register (0x00000008)
        3. 4.1.1.3 Linking RAM Region 0 Base Address Register (0x0000000C)
        4. 4.1.1.4 Linking RAM Region 0 Size Register (0x00000010)
        5. 4.1.1.5 Linking RAM Region 1 Base Address Register (0x00000014)
        6. 4.1.1.6 Free Descriptor/Buffer Starvation Count Register N (0x00000020 + N×4)
      2. 4.1.2 Queue Status RAM
      3. 4.1.3 Descriptor Memory Setup Region
        1. 4.1.3.1 Memory Region R Base Address Register (0x00000000 + 16×R)
        2. 4.1.3.2 Memory Region R Start Index Register (0x00000004 + 16×R)
        3. 4.1.3.3 Memory Region R Descriptor Setup Register (0x00000008 + 16×R)
      4. 4.1.4 Queue Management/Queue Proxy Regions
        1. 4.1.4.1 Queue N Register A (0x00000000 + 16×N)
        2. 4.1.4.2 Queue N Register B (0x00000004 + 16×N)
        3. 4.1.4.3 Queue N Register C (0x00000008 + 16×N)
        4. 4.1.4.4 Queue N Register D (0x0000000C + 16×N)
      5. 4.1.5 Queue Peek Region
        1. 4.1.5.1 Queue N Status and Configuration Register A (0x00000000 + 16×N)
        2. 4.1.5.2 Queue N Status and Configuration Register B (0x00000004 + 16×N)
        3. 4.1.5.3 Queue N Status and Configuration Register C (0x00000008 + 16×N)
        4. 4.1.5.4 Queue N Status and Configuration Register D (0x0000000C + 16×N)
    2. 4.2 Packet DMA
      1. 4.2.1 Global Control Registers Region
        1. 4.2.1.1 Revision Register (0x00)
        2. 4.2.1.2 Performance Control Register (0x04)
        3. 4.2.1.3 Emulation Control Register (0x08)
        4. 4.2.1.4 Priority Control Register (0x0C)
        5. 4.2.1.5 QMn Base Address Register (0x10, 0x14, 0x18, 0x1c)
      2. 4.2.2 TX DMA Channel Configuration Region
        1. 4.2.2.1 TX Channel N Global Configuration Register A (0x000 + 32×N)
        2. 4.2.2.2 TX Channel N Global Configuration Register B (0x004 + 32×N)
      3. 4.2.3 RX DMA Channel Configuration Region
        1. 4.2.3.1 RX Channel N Global Configuration Register A (0x000 + 32×N)
      4. 4.2.4 RX DMA Flow Configuration Region
        1. 4.2.4.1 RX Flow N Configuration Register A (0x000 + 32×N)
        2. 4.2.4.2 RX Flow N Configuration Register B (0x004 + 32×N)
        3. 4.2.4.3 RX Flow N Configuration Register C (0x008 + 32×N)
        4. 4.2.4.4 RX Flow N Configuration Register D (0x00C + 32×N)
        5. 4.2.4.5 RX Flow N Configuration Register E (0x010 + 32×N)
        6. 4.2.4.6 RX Flow N Configuration Register F (0x014 + 32×N)
        7. 4.2.4.7 RX Flow N Configuration Register G (0x018 + 32×N)
        8. 4.2.4.8 RX Flow N Configuration Register H (0x01C + 32×N)
      5. 4.2.5 TX Scheduler Configuration Region
        1. 4.2.5.1 TX Channel N Scheduler Configuration Register (0x000 + 4×N)
    3. 4.3 QMSS PDSPs
      1. 4.3.1 Descriptor Accumulation Firmware
        1. 4.3.1.1 Command Buffer Interface
        2. 4.3.1.2 Global Timer Command Interface
        3. 4.3.1.3 Reclamation Queue Command Interface
        4. 4.3.1.4 Queue Diversion Command Interface
      2. 4.3.2 Quality of Service Firmware
        1. 4.3.2.1 QoS Algorithms
          1. 4.3.2.1.1 Modified Token Bucket Algorithm
        2. 4.3.2.2 Command Buffer Interface
        3. 4.3.2.3 QoS Firmware Commands
        4. 4.3.2.4 QoS Queue Record
        5. 4.3.2.5 QoS Cluster Record
        6. 4.3.2.6 RR-Mode QoS Cluster Record
        7. 4.3.2.7 SRIO Queue Monitoring
          1. 4.3.2.7.1 QoS SRIO Queue Monitoring Record
      3. 4.3.3 Open Event Machine Firmware
      4. 4.3.4 Interrupt Operation
        1. 4.3.4.1 Interrupt Handshaking
        2. 4.3.4.2 Interrupt Processing
        3. 4.3.4.3 Interrupt Generation
        4. 4.3.4.4 Stall Avoidance
      5. 4.3.5 QMSS PDSP Registers
        1. 4.3.5.1 Control Register (0x00000000)
        2. 4.3.5.2 Status Register (0x00000004)
        3. 4.3.5.3 Cycle Count Register (0x0000000C)
        4. 4.3.5.4 Stall Count Register (0x00000010)
    4. 4.4 QMSS Interrupt Distributor
      1. 4.4.1 INTD Register Region
        1. 4.4.1.1  Revision Register (0x00000000)
        2. 4.4.1.2  End Of Interrupt (EOI) Register (0x00000010)
        3. 4.4.1.3  Status Register 0 (0x00000200)
        4. 4.4.1.4  Status Register 1 (0x00000204)
        5. 4.4.1.5  Status Register 2 (0x00000208)
        6. 4.4.1.6  Status Register 3 (0x0000020c)
        7. 4.4.1.7  Status Register 4 (0x00000210)
        8. 4.4.1.8  Status Clear Register 0 (0x00000280)
        9. 4.4.1.9  Status Clear Register 1 (0x00000284)
        10. 4.4.1.10 Status Clear Register 4 (0x00000290)
        11. 4.4.1.11 Interrupt N Count Register (0x00000300 + 4xN)
  6. 5Mapping Information
    1. 5.1 Queue Maps
    2. 5.2 Interrupt Maps
      1. 5.2.1 KeyStone I TCI661x, C6670, C665x devices
      2. 5.2.2 KeyStone I TCI660x, C667x devices
      3. 5.2.3 KeyStone II devices
    3. 5.3 Memory Maps
      1. 5.3.1 QMSS Register Memory Map
      2. 5.3.2 KeyStone I PKTDMA Register Memory Map
      3. 5.3.3 KeyStone II PKTDMA Register Memory Map
    4. 5.4 Packet DMA Channel Map
  7. 6Programming Information
    1. 6.1 Programming Considerations
      1. 6.1.1 System Planning
      2. 6.1.2 Notification of Completed Work
    2. 6.2 Example Code
      1. 6.2.1 QMSS Initialization
      2. 6.2.2 PKTDMA Initialization
      3. 6.2.3 Normal Infrastructure DMA with Accumulation
      4. 6.2.4 Bypass Infrastructure notification with Accumulation
      5. 6.2.5 Channel Teardown
    3. 6.3 Programming Overrides
    4. 6.4 Programming Errors
    5. 6.5 Questions and Answers
  8. AExample Code Utility Functions
  9. BExample Code Types
  10. CExample Code Addresses
    1. C.1 KeyStone I Addresses:
    2. C.2 KeyStone II Addresses:
  11.   Revision History
  12. IMPORTANT NOTICE
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USER'S GUIDE

KeyStone Architecture Multicore Navigator

Preface

The Multicore Navigator uses a Queue Manager Subsystem (QMSS) and a Packet DMA (PKTDMA) to control and implement high-speed data packet movement within the device. This reduces the traditional internal communications load on the device DSPs significantly, increasing overall system performance.

About This Manual

This document describes the functionality, operational details, and programming information for the PKTDMA and the components of the QMSS in KeyStone architecture devices.

Trademarks

All trademarks are the property of their respective owners.

Notational Conventions

This document uses the following conventions:

  • Commands and keywords are in boldface font.
  • Arguments for which you supply values are in italic font.
  • Terminal sessions and information the system displays are in screen font.
  • Information you must enter is in boldface screen font.
  • Elements in square brackets ([ ]) are optional.

Notes use the following conventions:

NOTE

Means reader take note. Notes contain helpful suggestions or references to material not covered in the publication.

The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.

CAUTION

Indicates the possibility of service interruption if precautions are not taken.

WARNING

Indicates the possibility of damage to equipment if precautions are not taken.

Related Documentation from Texas Instruments

Antenna Interface 2 (AIF2) for KeyStone Devices User Guide SPRUGV7
Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide SPRUGS2
Memory Protection Unit (MPU) for KeyStone Devices User Guide SPRUGW5
Packet Accelerator (PA) for KeyStone Devices User Guide SPRUGS4
Serial RapidIO (SRIO) for KeyStone Devices User Guide SPRUGW1

1 Introduction

1.1 Terminology Used in This Document

Table 1-1 defines the important acronyms used in this document.

Table 1-1 Terminology

Acronym Definition
AIF2 Antenna interface subsystem
BCP Bit coprocessor
CPPI Communications port programming interface (Multicore Navigator)
EOP End of packet
FFTC FFT coprocessor subsystem
FDQ Free descriptor queue
MOP Middle of packet
NETCP Network Coprocessor (new name for Packet Accelerator)
OEM Open event machine
PA, PASS Packet accelerator subsystem
PDSP Packed data structure processor
PKTDMA Packet DMA, consisting of two independent halves: RX DMA and TX DMA (previously was CDMA for CPPI DMA -- this is obsolete)
PS Protocol specific
QM, QMSS Hardware queue manager; queue manager sub-system
QoS Quality of service (PDSP firmware)
RX DMA RX half of the PKTDMA
SOP Start of packet
SRIO Serial rapid I/O subsystem
TX DMA TX half of the PKTDMA

1.2 KeyStone I Features

Multicore Navigator provides the following features in KeyStone I devices:

  • One hardware queue manager, including:
    • 8192 queues (some dedicated for specific use)
    • 20 descriptor memory regions
    • 2 linking RAMs (one internal to QMSS, supporting 16K descriptors)
  • Several PKTDMAs, located in the following subsystems:
    • QMSS (infrastructure, or core-to-core PKTDMA)
    • AIF2
    • BCP
    • FFTC (A, B, C)
    • NETCP (PA)
    • SRIO
  • Multi-core host notification via interrupt generation (accumulator functionality)

Multicore Navigator was developed based on the design goals while incorporating ideas from leading-edge architectures for Ethernet, ATM, HDLC, IEEE1394, 802.11, and USB communications modules.

Some general features of Multicore Navigator:

  • Centralized buffer management
  • Centralized packet queue management
  • Protocol-independent packet-level interface
  • Support for multi-channel / multi-priority queuing
  • Support for multiple free buffer queues
  • Efficient host interaction that minimizes host processing requirements
  • Zero copy packet handoff

Multicore Navigator provides the following services to the host:

  • Mechanism to queue an unlimited number of packets per channel
  • Mechanism to return buffers to host on packet transmit completion
  • Mechanism to recover queued buffers after transmit channel shut down
  • Mechanism to allocate buffer resources to a given receive port
  • Mechanism to pass buffers to host on completion of a packet reception
  • Mechanism to gracefully stop reception for receive channel shut down

1.3 KeyStone I Functional Block Diagram

Figure 1-1 shows the major functional components of Multicore Navigator for KeyStone I devices. The queue manager sub system (QMSS) contains a queue manager, the infrastructure PKTDMA, and two accumulator PDSPs with timers. The block marked Hardware Block is a Multicore Navigator peripheral (such as SRIO), and shows a detailed view of the PKTDMA sub-blocks with interfaces.

Figure 1-1 Multicore Navigator Block Diagram (KeyStone I)CPPI_Sim_Drawings.gif

1.4 KeyStone II Changes to QMSS

For KeyStone II devices, the following changes were made to the Queue Manager Sub System:

  • K2K, K2H only: Two hardware queue managers (QM1, QM2), including:
    • 8192 queues per queue manager
    • 64 descriptor memory regions per queue manager
    • 3 linking RAMs (one internal to QMSS, supporting 32K descriptors)
  • K2K, K2H only: Two infrastructure PKTDMAs (PKTDMA1 driven by QM1, PKTDMA2 driven by QM2)
  • Eight packed-data structure processors (PDSP1 to PDSP8), each with its own dedicated Timer module
  • Two interrupt distributors (INTD1, INTD2), which service two pairs of PDSPs.

These changes are shown in Figure 1-2. K2L and K2E devices do not contain QM2 or PKTDMA2, and have a 16K entry Linking RAM.

Figure 1-2 Queue Manager Sub System for KeyStone IIQueue_Manager_SS_for_Keystone_2.gif

1.5 KeyStone II QMSS Modes of Use

As described in the previous section, the KeyStone II QMSS is roughly a doubling of the modules in the KeyStone I QMSS. One component that was doubled in size, but not in number, is the internal linking RAM. Both QM1 and QM2 share this component. The programming of each QM’s linking RAM and descriptor memory region registers determines if the linking RAM is used cooperatively (Shared Mode) or independently (Split Mode).

1.5.1 Shared Mode

In this mode, both QMs share the entire internal linking RAM. Because both QMs will be writing into the same areas of the linking RAM, both QMs must be programmed with identical descriptor memory regions so that there will be no colliding indexes written into the linking RAM, which will corrupt it. The linking RAM registers in both QMs are also programmed identically, as shown in Figure 1-3. Advantage: The two QMs can be treated as a single double-sized KeyStone I QM.

Figure 1-3 Queue Manager Linking RAM — Shared Mode for KeyStone IIQueue_Manager_Linking_RAM_Shared_Mode_for_KS_2.gif

1.5.2 Split Mode

This is like having two independently operating KeyStone I QMs. In this mode, each QM has a non-overlapping partition of the linking RAM to use (not necessarily equal halves as shown here). This allows each QM to be programmed with descriptor memory regions that are independent of the other QM. Note that the descriptor region indexes must begin with 0 for each QM configuration, because the indexes are relative to the address given as the base of its linking RAM. Figure 1-1 shows the linking RAM configuration for this mode. Advantage: 128 total memory regions provides much better granularity of descriptor sizing/counts.

Figure 1-4 Queue Manager Linking RAM — Split Mode for KeyStone IIQueue_Manager_Linking_RAM_Split_Mode_for_KS_2.gif

 
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