Confirm the numerator, denominator, N divider, pre-divider and post-divider settings are correct for the DPLL and APLL. Refer to the LMK data sheet for the PFD, TDC, and VCO equations.

The LOFL status bit can falsely report an unlocked state due to improper threshold settings. Try widening the frequency lock threshold (see Table 2-24) by 10ppm to see if the LOFL status bit clears. Use TICS Pro to configure the threshold settings.

Confirm the DPLL is actually locked to the DPLL reference and not misreporting LOFL=0 by applying a small frequency offset (such as 1ppm to 5ppm) to either the APLL reference or the DPLL reference. Observe the impact on the output frequency. When the DPLL is locked and properly configured, the outputs have the same frequency accuracy as the DPLL reference. When the DPLL is not locked, the outputs have the same frequency accuracy as the APLL reference. Therefore, a frequency offset applied to the DPLL reference results in a frequency offset applied to the output clocks by the same amount when the DPLL is locked.

The following steps provide an example debug scenario with the results summarized in Table 2-19. In the example, the XO input is used as the APLL reference and the INx input is used as the DPLL reference. The "programmed frequency" refers to the configured register settings and the "expected output frequency" is the output frequency that is expected when measured.

The LMK device offers a status register, as seen in Table 2-23, to monitor the live APLL numerator value. When the DPLL is locked, the DPLL makes updates to the APLL numerator (at a rate defined by the TDC) until a 0ppm error between the DPLL reference and VCO output is attained. Since the DPLL reference has noise and jitter, the DPLL continuously makes corrections to the APLL numerator trying to achive a 0ppm error. Checking the live APLL numerator status for DPLL lock is similar to checking the tuning voltage (LFx pin) for APLL lock.

Use the following pseudocode to get the frequency error (ppb) between the expected and measured VCO frequency, where APLL_NUM_STAT is the APLL numerator status register readback value and APLL_N_DIV is the APLL N divider register readback value. The APLL N divider register address is listed in Table 2-21. Graph the results over the time to get a time interval error (TIE) plot. In a stable DPLL locked state, the frequency error is near 0ppb and does not sporadically drift in an uncontrolled manner.

get_APLL_NUM_STAT_as_ppb (phase_detect_freq, expected_vco_freq){
    numStatVal = Read_Reg("APLL_NUM_STAT")
    fract = numStatVal / (2^40)
    n_div = Read_Reg("APLL_N_DIV")
    meas_vco_freq = phase_detect_freq * (n_div + fract)
    ppb_error = 1e9 * ((meas_vco_freq – expected_vco_freq) / vco_freq)
    return ppb_error
}