SNAA421 November   2025 LMK05318B , LMK5B12204 , LMK5B33216 , LMK5B33414 , LMK5C33216A , LMK5C33414A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Start Here: Using TICS Pro for Configuration and Readback
    1. 1.1 TICS Pro Status Page
    2. 1.2 TICS Pro Default Setting
  5. 2Debug Procedure: From Device Start-Up to Locked Output State
    1. 2.1 Is the APLL Reference Valid?
      1. 2.1.1 Check Status of APLL Reference
      2. 2.1.2 Debug APLL Reference
    2. 2.2 Is the APLL Locked?
      1. 2.2.1 Check Status of APLL Lock
      2. 2.2.2 Debug APLL Lock
    3. 2.3 Is the DPLL Reference Valid?
      1. 2.3.1 Check Status of DPLL Reference Validation
      2. 2.3.2 Debug DPLL Reference Validation
    4. 2.4 Is the DPLL Selecting a Reference?
      1. 2.4.1 Check Status of DPLL Reference Selection
      2. 2.4.2 Debug DPLL Reference Selection
    5. 2.5 Is the DPLL Frequency Locked?
      1. 2.5.1 Check Status of DPLL Frequency Lock
      2. 2.5.2 Debug DPLL Frequency Lock
    6. 2.6 Is the DPLL Phase Locked?
      1. 2.6.1 Check Status of DPLL Phase Lock
      2. 2.6.2 Debug DPLL Phase Lock
  6. 3Summary
  7. 4References

2.3.1 Check Status of DPLL Reference Validation

The LMK device has a DPLL reference validation detector that checks the validity of the external DPLL reference input clock. The validity of the external DPLL reference is determined by the enabled detectors, outlined in Table 2-9. The status is reported by the "DPLL reference validation" bit, described in Table 2-13. Refer to Table 2-11 for the DPLL reference validation status registers in the LMK device families.

Note that the reference validation detectors do not apply to DPLL inputs that are sourced internally from a cascaded source. When using a cascaded source as the input, the reference validation bit is always 1 unless the upstream APLL is disabled or unlocked.

Table 2-9 Reference Validation Settings
DEVICE FAMILY REFERENCE VALIDATION SETTING DESCRIPTION
LMK05318B, LMK05318, LMK5B, LMK5CA, LMK5C Validation timer The setting is true when the DPLL reference remains valid (across all enabled detectors) for the time defined by the validation timer.
LMK05318B, LMK05318 Amplitude detector The setting is true when the voltage swing of the DPLL reference is higher than the defined amplitude threshold.
LMK05318B, LMK05318, LMK5B, LMK5CA, LMK5C Frequency detector The setting is true when the frequency error between DPLL reference and the XO input is within the valid threshold. If the frequency exceeds the invalid threshold, then the setting is false. Disable for 1PPS inputs.
LMK05318B, LMK05318, LMK5B, LMK5CA, LMK5C Early (runt pulse) and late (missing pulse) window detectors The setting is true when the period of the DPLL reference is less than the missing clock threshold and greater than the early clock threshold. Disable for 1PPS inputs.
LMK05318B, LMK05318, LMK5B, LMK5CA, LMK5C Phase valid monitor
(1PPS phase detector) 		The setting is true when the next clock edge of the DPLL reference is within the expected clock edge defined by the detector threshold. Enable only for 1PPS inputs.
Table 2-10 DPLL Reference Validation - Status Bit Definition
BIT STATE MEANING DESCRIPTION
0 Undesired result The DPLL reference valid bit is cleared when the DPLL reference does not meet the requirements of the enabled reference validation settings. At least one of the enabled reference detectors is failing (false).
1 Desired result The DPLL reference valid bit is set when the DPLL reference meets the requirements of the enabled reference validation settings. All of the enabled reference detectors must be passing (true).
Table 2-11 DPLL Reference Validation - Status Register
DEVICE FAMILY TICS PRO FIELD NAME DPLL REFERENCE VALID
REGISTER
LMK05318B, LMK05318 PRIREF_VALSTAT R411[2]
SECREF_VALSTAT R411[3]
LMK5B, LMK5CA, LMK5C REF0_VALID_STATUS R50[0]
REF1_VALID_STATUS R50[1]
REF2_VALID_STATUS(1) R50[2]
REF3_VALID_STATUS(1) R50[3]
(1) Only available on the 4-input devices.