SNAA421 November 2025 LMK05318B , LMK5B12204 , LMK5B33216 , LMK5B33414 , LMK5C33216A , LMK5C33414A
The LMK device has a DPLL reference selector that chooses one valid DPLL reference to use for DPLL lock. The selected DPLL input is reported through the "DPLL Reference Selection" status bits as described in Table 2-13. Table 2-11 shows the DPLL reference selection status registers for the LMK device families.
| BIT[n:0] STATE | MEANING | DESCRIPTION |
|---|---|---|
| 0 | Undesired result | The DPLL reference valid bit is cleared when the DPLL is in holdover. There is not one valid reference input and/or the DPLL register settings are incorrect. |
| > 0 | Desired result | The DPLL reference valid bit is greater than 0 when the DPLL is locked to the input clock specified by the status value.(1) There is at least one valid reference input. |
| DEVICE FAMILY | TICS PRO FIELD NAME | DPLL REFERENCE SELECTION REGISTER | ||
|---|---|---|---|---|
| BAW DPLL | DPLL2 | DPLL1(1) | ||
| LMK05318B, LMK05318 | DPLL_REFSEL_STAT | R167[1:0] | N/A | N/A |
| LMK5B, LMK5CA, LMK5C | DPLLx_REFSEL_STAT | R527[5:0] | R377[5:0] | R227[5:0] |