SNAA421 November   2025 LMK05318B , LMK5B12204 , LMK5B33216 , LMK5B33414 , LMK5C33216A , LMK5C33414A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Start Here: Using TICS Pro for Configuration and Readback
    1. 1.1 TICS Pro Status Page
    2. 1.2 TICS Pro Default Setting
  5. 2Debug Procedure: From Device Start-Up to Locked Output State
    1. 2.1 Is the APLL Reference Valid?
      1. 2.1.1 Check Status of APLL Reference
      2. 2.1.2 Debug APLL Reference
    2. 2.2 Is the APLL Locked?
      1. 2.2.1 Check Status of APLL Lock
      2. 2.2.2 Debug APLL Lock
    3. 2.3 Is the DPLL Reference Valid?
      1. 2.3.1 Check Status of DPLL Reference Validation
      2. 2.3.2 Debug DPLL Reference Validation
    4. 2.4 Is the DPLL Selecting a Reference?
      1. 2.4.1 Check Status of DPLL Reference Selection
      2. 2.4.2 Debug DPLL Reference Selection
    5. 2.5 Is the DPLL Frequency Locked?
      1. 2.5.1 Check Status of DPLL Frequency Lock
      2. 2.5.2 Debug DPLL Frequency Lock
    6. 2.6 Is the DPLL Phase Locked?
      1. 2.6.1 Check Status of DPLL Phase Lock
      2. 2.6.2 Debug DPLL Phase Lock
  6. 3Summary
  7. 4References

2.3.2 Debug DPLL Reference Validation

If the status is undesired, run through the following debug steps.

  1. Check the DPLL reference input termination.

    Confirm the correct input termination scheme is used (whether external or internal to the device). Test with different internal termination register settings. Refer to the LMK device data sheet or TICS Pro for guidance.

  2. Check the DPLL input signals by probing the external DPLL input pins.

    Confirm the measured frequency and voltage swing meet the DPLL reference input requirements from the Electrical Characteristics table in the LMK device data sheet. Measure the frequency using a frequency counter or phase noise analyzer. Avoid using an oscilliscope for frequency measurements as the inherent oscilliscope noise does not provide accurate readings. Measure the voltage swing using an oscilliscope.

  3. Check the DPLL inputs by probing the GPIO pins.

    Use the GPIO pins to view the DPLL inputs when probing the DPLL input pins is not easily possible. Configure the GPIOs as the "Reference Monitor Output Divided by 2" to apply a divide by 2 to the DPLL input path and reduce the GPIO output frequency. Refer to Table 2-12.

    Table 2-12 Reference Monitor R Divided by 2 - Register Setting
    DEVICE TICS PRO FIELD NAME PIN NAME REFERENCE MONITOR OUTPUT DIVIDED BY 2
    REGISTER SETTING
    REF0 or
    PRIREF    		 REF1 or
    SECREF    		 REF2(2) REF3(2)
    LMK05318B STATx_SEL
    (xxxREF Monitor Divider Output, div-by-2)    		 STATUS0 R48[6:0] = 0x0D R48[6:0] = 0x0E N/A N/A
    STATUS1 R49[6:0] = 0x0D R49[6:0] = 0x0E N/A N/A
    LMK5B or LMK5CA(1) GPIOx_SEL
    (REFx Monitor Divider Output Divided by 2)    		 Required for any GPIOx R70[0] = 1
    GPIO0 R57[6:0] = 0x59 R57[6:0] = 0x5A R57[6:0] = 0x5B R57[6:0] = 0x5C
    GPIO1 R58[6:0] = 0x59 R58[6:0] = 0x5A R58[6:0] = 0x5B R58[6:0] = 0x5C
    GPIO2 R59[6:0] = 0x59 R59[6:0] = 0x5A R59[6:0] = 0x5B R59[6:0] = 0x5C
    (1) To use the REF monitor on the GPIO pin, the DPLLx_REFy_AUTO_PRTY register for the respective REFy must be greater than 0. This is true for any input mux option selected (Auto Revertive, Auto Non-Revertive, Manual with Holdover, or Manual with Holdover).
    (2) Only available on the 4-input devices.
  4. Identify the failing reference validation detector.

    The DPLL reference validation can fail when at least one detector is not properly configured. To identify the failing detector, disable all of the reference valiation settings. Enable a validation setting one-by-one, checking the status bit after each enable until the failing detector is identified. Refer to the steps below for an example debug scenario. Additionally, try minimizing the validation timer to determine if the issue is intermittent and/or because the DPLL reference fails a longer validation window.

    1. From readback, the DPLL reference valid bit = 0.
    2. Disable all reference validation settings.
    3. Enable only the validation timer first.
    4. From readback, the DPLL reference valid bit = 1. This means the validation timer is not the issue.
    5. Enable also the early and late window detectors.
    6. From readback, the DPLL reference valid bit = 1. This means the early and late window detectors are not the issue.
    7. Enable also the frequency detector.
    8. From readback, the DPLL reference valid bit = 0. This means the frequency detector is the issue. The frequency thresholds need to be adjusted to account for the reference and XO frequency error.
    9. Increase the frequency detector valid and invalid thresholds.
    10. From readback, the DPLL reference valid bit = 1.
    11. The DPLL reference is valid with all the desired validation settings enabled.