The DPLL is considered phase locked when the APLL output clocks track the phase of the selected DPLL input. This is also known as phase synchronization. When phase-locked, the input and output clocks can be triggered to each other on an oscilliscope. There can be an offset present between the locked outputs and the selected DPLL input. The offset is programmable depending on the LMK device. Typically, the offset is small and subject to change after POR, software reset, hardware reset, or a hitless switch. Use zero-delay mode when a deterministic phase offset is required.

The LOPL status bit can falsely report an unlocked state due to improper threshold settings. A noisy DPLL reference or APLL reference with a narrow DPLL loop bandwidth can cause large phase variations. To account for such variations, widen the phase lock thresholds to allow the device to be considered phase locked. Use TICS Pro to configure the threshold settings.

The miminum and maximum TDC debug registers can be readback as listed in Table 2-25. Configure the TDC debug register as specified in Table 2-26.

Use the pseudocode below to capture the phase error measured by the TDC of the device. Note that the readback value is a digital number (unitless). The readback rate of the minimum and maximum TDC registers must be no faster than the configured TDC rate. If the readback rate is faster than the TDC rate, a 0 value is readback. Graph the results over the time. In a stable DPLL locked state, the TDC reaches a near 0 value and does not sporadically change in an uncontrolled manner.

dpll_config_R207 = # DEFINED BY ENABLE SETTING TABLE

def setup_tdc_readback():    
    WriteReg(R208,0x01)                
    WriteReg(R207, dpll_config_R207)    

def get_tdc_min_max():    
    # Read MSB to LSB.  Min/max reset after R206 is read.
    rawTDC_MIN = ReadReg(R191, R198)    
    rawTDC_MAX = ReadReg(R199, R206)    
    
    val = sum([(2**(56-(8*i)))* rawTDC_MIN[i] for i in range(8)])
    if  rawTDC_MIN[0] > 127:
        val ^= 0xffffffffffffffff
        val &= 0xffffffffffffffff
        val += 1
        val *= -1
    TDC_MIN = val
 
    val = sum([(2**(56-(8*i)))*rawTDC_MAX[i] for i in range(8)])
    if rawTDC_MAX[0] > 127:
        val ^= 0xffffffffffffffff
        val &= 0xffffffffffffffff
        val += 1
        val *= -1
    TDC_MAX = val
 
    return (TDC_MIN, TDC_MAX)

One way to check the inputs to the TDC is by configuring the GPIO status pins as the "DPLL R divided by 2" and "DPLL FB divided by 2" signals. The two signals represent the DPLL R divider and DPLL FB divider paths with a divide by 2 on each signal. Route the two TDC input signals to a scope to determine the DPLL lock state. If the DPLL FB clock is a drifting clock compared to the DPLL R clock, then the DPLL settings (such as for the TDC and DLF) is possibly not configured properly. Contact TI as the next step by posting on the public TI E2E forum, include the TICS Pro configuration file (.tcs) with oscilloscope screenshots capturing the FB and R waveforms. Otherwise, if the DPLL FB clock is triggered to the DPLL R clock and not drifting, then the DPLL is locked and properly configured. The LOPL flag can be false reporting due to improper LOPL threshold settings. Increase the lock and unlock thresholds until the LOPL flag clears.

The equations for each signal are represented by Equation 1 and Equation 2.

For example, the "DPLL R divide by 2" signal frequency is 0.625MHz for a DPLL reference frequency of 156.25MHz and an R divider value of 125 as shown in Equation 3.

The registers for the DPLL R divided by 2 and FB divided by 2 signals are listed in Table 2-27 and Table 2-28.