SLVAEF4C august   2019  – may 2023 TPS7H4001-SP

PRODUCTION DATA  

  1.   1
  2.   Single-Event Effects Test Report of the TPS7H4001-SP
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Events Effects (SEE)
  6. 3 Test Device and Evaluation Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Safe-Operating-Area (SOA) Results
    2. 7.2 Single Event Latch-Up (SEL) Results
    3. 7.3 Single-Event-Burnout (SEB) and Single-Event-Gate-Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Summary
  13. 10Total Ionizing Dose (TID) From SEE Experiments
  14. 11References
  15. 12Revision History

2 Single-Events Effects (SEE)

The primary concern for the TPS7H4001-SP is the robustness against the destructive single event effects (DSEE). The principal destructive effects studied here are:

  • Single-event latch-up (SEL)
  • Single-event burn-out (SEB)
  • Single-event gate rupture (SEGR)

The TPS7H4001-SP is DSEE-free when operated within the safe-operating-area (SOA). The SOA curve has been validated up to a LETEFF = 75 MeV·cm2/mg, using a total of 37 TPS7H4001-SP RHA qualified devices.

In mixed technologies such as the BiCMOS process used on the TPS7H4001-SP, the CMOS circuitry introduces a potential for SEL susceptibility. SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-substrate and n-well and n+ and p+ contacts) [1,2]. If formed, the parasitic bipolar structure creates a high-conductance path (creating a steady-state current that typically is orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. When the TPS7H4001-SP is operated within its Safe-Operating-Area (SOA), as shown in Figure 7-1, the device is DSEE-free.

Since this device is designed to conduct large currents (up to 18 A) and withstand up to 7 V during the off state, the power LDMOS (P-type and N-Type, switching FETs) introduces a potential susceptibility for SEB and SEGR [3]. The TPS7H4001-SP was evaluated for destructive effects at die temperatures of 20°C and 60°C, under enabled (switching) and disabled modes. The device was evaluated at full load conditions and maximum voltage. Since it has been shown that the MOSFET is susceptible to burn-out decrement with temperature [4], the device was evaluated when operated under room temperature (RT) and with external cooling. The devices were cooled-down (or "chilled") by using VORTEC Tube (Model 611). The TPS7H4001-SP when operated within the SOA, as shown in Figure 7-1, is DSEE-free.

Under heavy-ions, the TPS7H4001-SP exhibits three transient modes that are fully recoverable without the need for external intervention. Characterized at room temperature and elevated temperature (125°C). The three observed transients are:

  • A brief false PWRGD transient (referred to here as a PWRGDSET) typically of 3 μs, indicating a non-stable output voltage even when the VOUT voltage was properly regulated. PWRGD is an open drain digital flag that indicates the status of the output regulation. By design when the voltage is within a window of 9% of the reference the PWRGD becomes high Impedance (or open). However under heavy-ion this flag was being momentarily pulled down (activated), as an indication of a voltage regulation fault. This kind of SET can be filtered out by the use of an small R-C filter, as shown in Figure 8-5.
  • A brief transient of the output voltage (referred to here as VOUTSET). For the purpose of this report the transients were characterize for deviations ≥ |±3%| from the nominal output voltage of ≈1 V (±30 mV). These upsets typically have duration of 16 μs and 3.63% deviation from the nominal voltage. For more details, see Section 8.
  • A soft-start power re-cycle, which results in the VOUT dropping near zero volts and characterized by a recovery time governed by the soft-start (SS) capacitor. These variety of SETs are referred to here as SSSET. It is important to notice that upsets of this kind were observed only at elevated temperatures (125°C). Not a single SSSET was observed at room temperature or during the cool down testing (during the SEB testing).