SLAA419C October   2009  – April 2019 MSP430F5418 , MSP430F5418A , MSP430F5419 , MSP430F5419A , MSP430F5435 , MSP430F5435A , MSP430F5436 , MSP430F5436A , MSP430F5437 , MSP430F5437A , MSP430F5438 , MSP430F5438A

 

  1.   Migrating From MSP430F541x and MSP430F543x MCUs to MSP430F541xA and MSP430F543xA MCUs
    1.     Trademarks
    2. 1 Device Comparison
    3. 2 Hardware Considerations
      1. 2.1 PMM Settings and Low Power Consumption
      2. 2.2 Operating Frequency vs Supply Voltage
      3. 2.3 Internal Voltage Reference
      4. 2.4 Unified Clock System (UCS) Settings
      5. 2.5 Cyclic Redundancy Check Module
      6. 2.6 Device Errata
    4. 3 Firmware Considerations
      1. 3.1 PMM Default States
        1. 3.1.1 PMM Defaults for F543x
          1. 3.1.1.1 Power Management Module Control Register 0 (PMMCTL0)
          2. 3.1.1.2 Supply Voltage Supervisor and Monitor High-Side Control Register (SVSMHCTL)
          3. 3.1.1.3 Supply Voltage Supervisor and Monitor Low-Side Control Register (SVSMLCTL)
          4. 3.1.1.4 Power Management Module Reset and Interrupt Enable Register (PMMRIE)
        2. 3.1.2 PMM Defaults for F543xA
      2. 3.2 Internal Voltage Reference
        1. 3.2.1 ADC12 Temperature Sensor Equation
      3. 3.3 Bootloader (BSL)
    5. 4 References
  2.   Revision History

2.4 Unified Clock System (UCS) Settings

The logic for the Unified Clock System (UCS) has changed slightly for A revisions of silicon. The changes generally affect the conditions under which the four available reference oscillators, the reference oscillator (REFO), the very low frequency oscillator (VLO), and the two crystal oscillators (XT1 and XT2) are enabled or disabled. These differences are outlined extensively in the UCS chapter of the MSP430F5xx and MSP430F6xx Family User's Guide and should be reviewed for possible optimizations to the UCS configuration and overall power consumption. Existing UCS code should require no modification for proper execution.