SLAA419C October   2009  – April 2019 MSP430F5418 , MSP430F5418A , MSP430F5419 , MSP430F5419A , MSP430F5435 , MSP430F5435A , MSP430F5436 , MSP430F5436A , MSP430F5437 , MSP430F5437A , MSP430F5438 , MSP430F5438A

 

  1.   Migrating From MSP430F541x and MSP430F543x MCUs to MSP430F541xA and MSP430F543xA MCUs
    1.     Trademarks
    2. 1 Device Comparison
    3. 2 Hardware Considerations
      1. 2.1 PMM Settings and Low Power Consumption
      2. 2.2 Operating Frequency vs Supply Voltage
      3. 2.3 Internal Voltage Reference
      4. 2.4 Unified Clock System (UCS) Settings
      5. 2.5 Cyclic Redundancy Check Module
      6. 2.6 Device Errata
    4. 3 Firmware Considerations
      1. 3.1 PMM Default States
        1. 3.1.1 PMM Defaults for F543x
          1. 3.1.1.1 Power Management Module Control Register 0 (PMMCTL0)
          2. 3.1.1.2 Supply Voltage Supervisor and Monitor High-Side Control Register (SVSMHCTL)
          3. 3.1.1.3 Supply Voltage Supervisor and Monitor Low-Side Control Register (SVSMLCTL)
          4. 3.1.1.4 Power Management Module Reset and Interrupt Enable Register (PMMRIE)
        2. 3.1.2 PMM Defaults for F543xA
      2. 3.2 Internal Voltage Reference
        1. 3.2.1 ADC12 Temperature Sensor Equation
      3. 3.3 Bootloader (BSL)
    5. 4 References
  2.   Revision History

2.1 PMM Settings and Low Power Consumption

The FLASH28 erratum for the F543x MCUs reports read disturb problems when the Power Management Module (PMM) VCORE levels are <2 (PMMCOREVx = 10b). This limitation makes it necessary for the device VCORE be initialized to level 2 in the boot code, which is different from the expected default values of level 0 specified in the MSP430F5xx and MSP430F6xx Family User's Guide. The higher voltage applied to the core increases the power consumption in active and low-power modes. To prevent a condition in which the read-disturb problem negatively affects the application flow, the user should not lower the VCORE level in attempts to obtain lower power consumption.

The F543xA can operate at all PMM levels, allowing for even lower current consumption than its predecessor. For example, in LFXT1 standby mode (LPM3 using a 32-kHz watch crystal), the standby current consumption of an F543xA MCU is approximately 1.9 µA, compared to approximately 2.7 µA for an F543x MCU. This is a considerable advantage for applications that spend the majority of their time in standby mode.

LPM4.5 support has been added to the F543xA. LPM4.5 is equivalent to LPM4, except that the internal voltage regulator is disabled. All CPU operations, clocks, and peripherals are disabled in LPM4.5. LPM4.5 can be leveraged like LPM4 in previous MSP430™ MCUs, because it achieves the lowest power consumption and is intended for shelf-life applications or applications that must sit in the lowest-power mode for very long periods of time without any peripheral activity. The contents of RAM are cleared (including all peripheral initializations) when entering LPM4.5, and the device must trigger a BOR to wake into an active mode. This BOR can be triggered by the removal of power, by using the RST line, or through the use of a port interrupt. The ability to use port interrupts adds flexibility to the hardware design in that more than one pin is available for wakeup from LPM4.5 so external hardware resources can wake the device.