ZHCS089G February   2011  – September 2017 TPS65185

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Data Transmission
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
      2. 8.3.2  Dependencies Between Rails
      3. 8.3.3  Soft Start
      4. 8.3.4  Active Discharge
      5. 8.3.5  VPOS/VNEG Supply Tracking
      6. 8.3.6  V3P3 Power Switch
      7. 8.3.7  VCOM Adjustment
        1. 8.3.7.1 Kick-Back Voltage Measurement
        2. 8.3.7.2 Storing the VCOM Power-Up Default Value in Memory
      8. 8.3.8  Fault Handling And Recovery
      9. 8.3.9  Power Good Pin
      10. 8.3.10 Interrupt Pin
      11. 8.3.11 Panel Temperature Monitoring
        1. 8.3.11.1 NTC Bias Circuit
        2. 8.3.11.2 Hot, Cold, and Temperature-Change Interrupts
        3. 8.3.11.3 Typical Application of the Temperature Monitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 SLEEP
      2. 8.4.2 STANDBY
      3. 8.4.3 ACTIVE
      4. 8.4.4 Mode Transitions
        1. 8.4.4.1 SLEEP → ACTIVE
        2. 8.4.4.2 SLEEP → STANDBY
        3. 8.4.4.3 STANDBY → ACTIVE
        4. 8.4.4.4 ACTIVE → STANDBY
        5. 8.4.4.5 STANDBY → SLEEP
        6. 8.4.4.6 ACTIVE → SLEEP
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
    6. 8.6 Register Maps
      1. 8.6.1  Thermistor Readout (TMST_VALUE) Register (address = 0x00h) [reset = N/A]
        1. Table 3. TMST_VALUE Register Field Descriptions
      2. 8.6.2  Enable (ENABLE) Register (address = 0x01h) [reset = 0h]
        1. Table 4. ENABLE Register Field Descriptions
      3. 8.6.3  Voltage Adjustment (VADJ) Register (address = 0x02h) [reset = 23h]
        1. Table 5. VADJ Register Field Descriptions
      4. 8.6.4  VCOM 1 (VCOM1) Register (address = 0x03h) [reset = 7Dh]
        1. Table 6. VCOM1 Register Field Descriptions
      5. 8.6.5  VCOM 2 (VCOM2) Register (address = 0x04h) [reset = 04h]
        1. Table 7. VCOM2 Register Field Descriptions
      6. 8.6.6  Interrupt Enable 1 (INT_EN1) Register (address = 0x05h) [reset = 7Fh]
        1. Table 8. INT_EN1 Register Field Descriptions
      7. 8.6.7  Interrupt Enable 2 (INT_EN2) Register (address = 0x06h) [reset = FFh]
        1. Table 9. INT_EN2 Register Field Descriptions
      8. 8.6.8  Interrupt 1 (INT1) Register (address = 0x07h) [reset = 0h]
        1. Table 10. INT1 Register Field Descriptions
      9. 8.6.9  Interrupt 2 (INT2) Register (address = 0x08h) [reset = N/A]
        1. Table 11. INT2 Register Field Descriptions
      10. 8.6.10 Power-Up Sequence 0 (UPSEQ0) Register (address = 0x09h) [reset = E4h]
        1. Table 12. UPSEQ0 Register Field Descriptions
      11. 8.6.11 Power-Up Sequence 1 (UPSEQ1) Register (address = 0x0Ah) [reset = 55h]
        1. Table 13. UPSEQ1 Register Field Descriptions
      12. 8.6.12 Power-Down Sequence 0 (DWNSEQ0) Register (address = 0x0Bh) [reset = 1Eh]
        1. Table 14. DWNSEQ0 Register Field Descriptions
      13. 8.6.13 Power-Down Sequence 1 (DWNSEQ1) Register (address = 0x0Ch) [reset = E0h]
        1. Table 15. DWNSEQ1 Register Field Descriptions
      14. 8.6.14 Thermistor 1 (TMST1) Register (address = 0x0Dh) [reset = 20h]
        1. Table 16. TMST1 Register Field Descriptions
      15. 8.6.15 Thermistor 2 (TMST2) Register (address = 0x0Eh) [reset = 78h]
        1. Table 17. TMST2 Register Field Descriptions
      16. 8.6.16 Power Good Status (PG) Register (address = 0x0Fh) [reset = 0h]
        1. Table 18. PG Register Field Descriptions
      17. 8.6.17 Revision and Version Control (REVID) Register (address = 0x10h) [reset = 45h]
        1. Table 19. REVID Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.11.1 NTC Bias Circuit

Figure 23 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an internally generated 2.25-V reference voltage through an integrated 7.307-kΩ bias resistor. A 43-kΩ resistor is connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.

Table 1. ADC Output Value vs Temperature

TEMPERATURE TMST_VALUE[7:0]
< –10°C 1111 0110
–10°C 1111 0110
–9°C 1111 0111
... ...
–2°C 1111 1110
–1°C 1111 1111
0°C 0000 0000
1°C 0000 0001
2°C 0000 0010
... ...
25°C 0001 1001
...
85°C 0101 0101
> 85°C 0101 0101
TPS65185 TPS651851 ntc_bias_lvsaq8.gifFigure 23. NTC Bias and Measurement Circuit

A temperature measurement is triggered by setting the READ_THERM bit of the TMST1 register to 1.During the A/D conversion the CONV_END bit of the TMST1 register reads 0, otherwise it reads 1. At the end of the A/D conversion the EOC bit in the INT2 register is set and the temperature value is available in the TMST_VALUE register.