ZHCS979F June   2012  – October 2020 TPS53318 , TPS53319

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
    7. 7.7 TPS53319 Typical Characteristics
    8. 7.8 TPS53318 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  5-V LDO and VREG Start-Up
      2. 8.3.2  Adaptive On-Time D-CAP Control and Frequency Selection
      3. 8.3.3  Ramp Signal
      4. 8.3.4  Adaptive Zero Crossing
      5. 8.3.5  Output Discharge Control
      6. 8.3.6  Power-Good
      7. 8.3.7  Current Sense, Overcurrent, and Short Circuit Protection
      8. 8.3.8  Overvoltage and Undervoltage Protection
      9. 8.3.9  Redundant Overvoltage Protection (OVP)
      10. 8.3.10 UVLO Protection
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Small Signal Model
      13. 8.3.13 External Component Selection Using All Ceramic Output Capacitors
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable, Soft Start, and Mode Selection
      2. 8.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 8.4.3 Forced Continuous Conduction Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Using Bulk Output Capacitors, Redundant Overvoltage Protection Function (OVP) Disabled
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step One: Select Operation Mode and Soft-Start Time
          2. 9.2.1.2.2 Step Two: Select Switching Frequency
          3. 9.2.1.2.3 Step Three: Choose the Inductor
          4. 9.2.1.2.4 Step Four: Choose the Output Capacitor or Capacitors
          5. 9.2.1.2.5 Step Five: Determine the Value of R1 and R2
          6. 9.2.1.2.6 Step Six: Choose the Overcurrent Setting Resistor
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Using Ceramic Output Capacitors, Redundant Overvoltage Protection Function (OVP) Enabled
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 External Component Selection Using All Ceramic Output Capacitors
          2. 9.2.2.2.2 Redundant Overvoltage Protection
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8.4.1 Enable, Soft Start, and Mode Selection

When the EN pin voltage rises above the enable threshold voltage (typically 1.3 V), the controller enters its start-up sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The controller calibrates the switching frequency setting resistance attached to the RF pin during the first 250 μs. It then stores the switching frequency code in the internal registers. During this period, the MODE pin also senses the resistance attached to this pin and determines the soft-start time. Switching is inhibited during this phase. In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the output voltage is maintained during start-up regardless of load current.

Note:

Enable voltage should not higher then VREG for 0.8 V.

Table 8-3 Soft-Start and MODE Settings
MODE SELECTIONACTIONSOFT-START TIME
(tSS) (ms)		RMODE (kΩ)
Auto SkipPull down to GND0.739
1.4100
2.8200
5.6475
Forced CCM(1)Connect to PGOOD0.739
1.4100
2.8200
5.6475
(1) Device enters FCCM after the PGOOD pin goes high when MODE is connected to PGOOD through the resistor RMODE.

After the soft-start period begins, the MODE pin becomes the input of an internal comparator which determines auto skip or FCCM mode operation. If MODE voltage is higher than 1.3 V, the converter enters into FCCM mode. Otherwise it operates in auto skip mode at light-load condition. Typically, when FCCM mode is selected, the MODE pin connects to the PGOOD pin through the RMODE resistor, so that before PGOOD goes high, the converter remains in auto skip mode.