ZHCSS95B march   2022  – may 2023 TPS389006-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006-Q1 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics

At 2.6 V <= VDD <= 5.5 V, NIRQ Voltage = 10 kΩ to VDD, NIRQ load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD= 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage  2.6 5.5 V
VDDUVLO Rising Threshold 2.67 2.81 V
Falling Threshold 2.48 2.60 V
VPOR Power on Reset Voltage (2) 1.65 V
IDD_Active Supply current into VDD pin (MON = LF/HF active)
ACT = High, Sleep = High 
 		 VDD <= 5.5V  1.55 2 mA
IDD_Sleep Supply current into VDD pin (MON = LF/HF active)
ACT = High ,Sleep = Low,I2C = Sleep power bit set to 1		 VDD <= 5.5V  1.55 2 mA
IDD_Idle Supply current into VDD pin (MON = OVLF active)
ACT = Low, Idle state-I2C active and OVLF mon		 VDD <= 5.5V 
>10ms BIST		 200 280 µA
IDD_Deep Sleep Supply current into VDD pin (MON = HF active), ACT = High,Sleep = Low,I2C = Sleep power bit set to 0 VDD <= 5.5V  275 380 µA
VMONX MON voltage range 0.2 5.5 V
IMONX Input current MONx pins VMON = 5V 20 µA
IMONX_ADJ Input current for ADJ version (1x) VMON = 5V 0.1 µA
VMON_LF 1x mode (No scaling) 0.2 1.475 V
with 4x scaling 0.8 5.5 V
VMON_HF 1x mode (No scaling) 0.2 1.475 V
with 4x scaling 0.8 5.5 V
Threshold granularity_HF 1x mode (No scaling) LSB 5 mV
4x mode (With scaling) LSB 20 mV
LPF cutoff LF Range of Programmable values (I2C selectable) Low Freq channel 250 4000 Hz
LPF cutoff HF High Freq channel 4 Mhz
Accuracy_HF VMON 0.2V≤VMONX≤1.0V –6 6 mV
1.0V<VMONX≤1.475V  -7.5 7.5 mV
1.475V<VMONX≤2.95V  -0.6 0.6 %
VMONX>2.95V  -0.7 0.7 %
VHYS_HF Hysteresis on UV,OV pin(Hysteresis is with respect of the tripoint ((UV),(OV))(1) 0.2V≤VMONX≤1.475V  5 11 mV
1.475V<VMONX≤2.95V  9 16
VMONX>2.95V 17 28 mV
MON_OFF OFF Voltage threshold Monitored falling edge of VMON 140 215 mV
ILKG Output leakage current -NIRQ VDD=VNIRQ=5.5V 300 nA
ACT_L Logic Low input  DEV_CONFIG.SOC_IF1=1 0.36 V
ACT_H Logic high input  DEV_CONFIG.SOC_IF1=1 0.84 V
SLEEP_L Logic Low input  DEV_CONFIG.SOC_IF1=1 0.36 V
SLEEP_H Logic high input  DEV_CONFIG.SOC_IF1=1 0.84 V
SYNC_L Input High DEV_CONFIG.SOC_IF1=1 0.36 V
SYNC_H Input Low DEV_CONFIG.SOC_IF1=1 0.84 V
SYNC_PU Internal Pull-up 25 100 kΩ
SYNC_OL with 10kΩ external pull up 0.1 V
ACT Internal Pull down 100 kΩ
SLEEP Internal Pull down 100 kΩ
UV,OV Steps/Resolution 0.2V<VMONX≤1.475V 5 mV
0.8V<VMONX<5.5V 20
VOL Low level output voltage-NIRQ NIRQ ,5.5V/5mA 100 mV
Ilkg(OD) Open-Drain output leakage current-NIRQ NIRQ pin in High Impedance,VNIRQ = 5.5, Not asserted state 90 nA
IADDR ADDR pin current 20 µA
I2C ADDR (Hex format) R=5.36k 0x30
R=16.2k 0x31
R=26.7k 0x32
R=37.4k 0x33
R=47.5k 0x34
R=59.0k 0x35
R=69.8k 0x36
R=80.6k 0x37
TSD Thermal Shutdown 155 ℃
TSD Hys Thernal Shutdown Hysterisis 20 ℃
RS Remote sense range -100 100 mV
ADC SPECIFICATION
Vin Input Range 0.2 5.5 V
Res_LF Resolution  1x mode (No scaling) 5 mV
4x mode 20 mV
fS Sample Rate 125 ksps
VHYS_LF Hysteresis LF faults 1x mode (No scaling) 10 15 mV
VHYS_LF Hysteresis LF faults 4x mode 40 55 mV
Accuracy_LF VMON 1x mode (No scaling) -12 +12 mV
4x mode -40 +40 mV
I2C ELECTRICAL SPECIFICATIONS
CB Capacitive load for SDA and SCL 400 pF
SDA,SCL Low Threshold DEV_CONFIG.SOC_IF1=0 0.8 V
SDA,SCL High Threshold DEV_CONFIG.SOC_IF1=0 2.0 V
(1) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).
(2) VPOR is the minimum VDDX voltage level for a controlled output state.