SPRS565D April 2009 – June 2014 TMS320C6743
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
The device has one PLL controller that provides clock to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
The various clock outputs given by the controller are as follows:
Various dividers that can be used are as follows:
Various other controls supported are as follows: