ZHCSLM6A december 2021 – june 2023 TDP0604
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Redriver | ||||||
fHDMI14_open | Maximum HDMI 1.4 clock frequency at which TX termination is assured to be open | HDMI1.4; 25 MHz ≤ IN_CLK ≤ 340 MHz; TXTERM_AUTO_HDMI14 = 0h; TERM = 2h; TX is DC-coupled; | 165 | MHz | ||
fHDMI14_300 | Minimum HDMI 1.4 clock frequency at which TX termination is assured to be 300-ohms | HDMI1.4; 25 MHz ≤ IN_CLK ≤ 340 MHz; TXTERM_AUTO_HDMI14 = 0h; TERM = 2h; TX is DC-coupled; | 250 | MHz | ||
tPD | Propagation delay time | At TTP4; | 90 | 220 | ps | |
tSK1(T) | Clock lane Intra-pair output skew with zero intra-pair skew at inputs | At TTP4; No intra-pair skew at input; 6 Gbps with 150 MHz clock; TX termination 100-Ω; Limited mode; | 0.10 | 0.15 | UI | |
tSK1(T) | Data lane Intra-pair output skew with zero intra-pair skew at inputs | At TTP4; No intra-pair skew at input; At 6 Gbps; TX termination 100-Ω; Limited mode; | 0.035 | 0.09 | UI | |
tSK2(T) | Inter-pair output skew | At TTP4; At 6 Gbps; | 30 | ps | ||
tRF-CLK-14 | Transition time (rise and fall time) for clock lane when operating at HDMI1.4 | At TTP4; 20% to 80%; Clock Frequency = 300 MHz; | 75 | 600 | ps | |
tRF-CLK-20 | Transition time (rise and fall time) for clock lane when operating at HDMI 2.0 | At TTP4; 20% to 80%; Clock Frequency = 150 MHz; | 75 | 600 | ps | |
tRF_14 | Transition time (rise and fall time) for data lanes when operating at HDMI 1.4 | At TTP4; 20% to 80%; DR = 3 Gbps; SLEW_HDMI14 = default; PRBS7 pattern; Clock Frequency = 300 MHz; | 75 | 195 | ps | |
tRFDAT_20 | Transition time (rise and fall time) for data lanes when operating at HDMI 2.0 | At TTP4; 20% to 80%; DR = 6 Gbps; SLEW_HDMI20 = default; PRBS7 pattern; Clock Frequency = 150 MHz; | 42.5 | 115 | ps | |
tTRANS_3G | Transition bit duration when de-emphasis/pre-emphasis is enabled | At TTP4; DR = 3 Gbps; Clock pattern of 128 zeros followed by 128 ones; | 0.4 | 1 | UI | |
tTRANS_6G | Transition bit duration when de-emphasis/pre-emphasis is enabled | At TTP4; DR = 6 Gbps; Clock pattern of 128 zeros followed by 128 ones; | 0.4 | 1 | UI | |
HPD | ||||||
tHPD_PD | HPD_IN to HPD_OUT propagation delay | Refer to Figure 7-7 | 100 | µs | ||
tHPD_PWRDOWN | HPD_IN debounce time before declaring Powerdown. Enter Powerdown if HPD_IN is low after debounce time. | Refer to Figure 7-7 | 2 | 4 | ms | |
tHPD_STANDBY | HPD_IN debounce time required for exiting Powerdown to Standby. Exit Powerdown if HPD_IN is high after debounce time. | Refer to Figure 7-8 | 2 | 4 | ms | |
Standby | ||||||
tSTANDBY_ENTRY | Detection of electrical idle to entry into Standby. | HPD_IN = H; | 300 | µs | ||
tSIGDET_DB | Maximum differential signal glitch time rejected during debounce before transitioning from standby to active | HPD_IN = H; | 25 | µs | ||
tSIGDET_DB | Maximum differential signal glitch time rejected during debounce before transitioning from active to standby | HPD_IN = H; | 50 | ns | ||
tSTANDBY_EXIT | Detection of differential signal to exit from Standby to Active state | HPD_IN = H; | 200 | µs | ||
fSCL | DDC buffer frequency | 100 | kHz | |||
tPLH1 | Propagation delay time. Low-to-high-level output. VIO set to 1.2 V LVCMOS levels. | LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 1400 | ns | ||
Propagation delay time. Low-to-high-level output. VIO set to 1.8 V LVCMOS levels. | LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 1400 | ns | |||
Propagation delay time. Low-to-high-level output. VIO set to 3.3 V LVCMOS levels. | LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 1400 | ns | |||
tPLH2 | Propagation delay time. Low-to-high-level output. VIO set to 1.2 V LVCMOS levels. | HV to LV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 410 | ns | ||
Propagation delay time. Low-to-high-level output. VIO set to 1.8 V LVCMOS levels. | HV to LV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 410 | ns | |||
Propagation delay time. Low-to-high-level output. VIO set to 3.3 V LVCMOS levels. | HV to LV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 410 | ns | |||
tPHL1 | Propagation delay time. High to low-level output. VIO set to 1.2 V LVCMOS. | LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 1200 | ns | ||
Propagation delay time. High to low-level output. VIO set to 1.8 V LVCMOS. | LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 1200 | ns | |||
Propagation delay time. High to low-level output. VIO set to 3.3 V LVCMOS. | LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 1200 | ns | |||
tPHL2 | Propagation delay time. High to low-level output. VIO set to 1.2 V LVCMOS. | HV to LV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 535 | ns | ||
Propagation delay time. High to low-level output. VIO set to 1.8 V LVCMOS. | HV to LV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 535 | ns | |||
Propagation delay time. High to low-level output. VIO set to 3.3 V LVCMOS. | HV to LV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; | 535 | ns | |||
tLV_FALL | LV side fall time for 1.2-V LVCMOS | 70% to 30%; CLV_BUS = CHV_BUS = 50 pF; | 75 | 260 | ns | |
LV side fall time for 1.8-V LVCMOS | 70% to 30%; CLV_BUS = CHV_BUS = 50 pF; | 75 | 260 | ns | ||
LV side fall time for 3.3-V LVCMOS | 70% to 30%; CLV_BUS = CHV_BUS = 50 pF; | 75 | 260 | ns | ||
tHV_FALL | HV side fall time | 70% to 30%; CLV_BUS = CHV_BUS = 50 pF; | 75 | 260 | ns | |
tLV_RISE | LV side rise time for 1.2-V LVCMOS | 30% to 70%; CLV_BUS = CHV_BUS = 50 pF; Pulled up to VIO using RPULV; | 300 | 670 | ns | |
LV side rise time for 1.8-V LVCMOS | 30% to 70%; CLV_BUS = CHV_BUS = 50 pF; Pulled up to VIO using RPULV; | 300 | 670 | ns | ||
LV side rise time for 3.3-V LVCMOS | 30% to 70%; CLV_BUS = CHV_BUS = 50 pF; Pulled up to VIO using RPULV; | 300 | 670 | ns | ||
tHV_RISE_50pF | HV side rise time (50 pF load) | 30% to 70%; CLV_BUS = CHV_BUS = 50 pF; VCC = 3.0 V; HDMI5V = 5.3 V; Pulled up to HDMI5V using RPUHV; | 225 | ns | ||
tHV_RISE_750pF | HV side rise time (750 pF load) | 30% to 70%; CLV_BUS = 50 pF; CHV_BUS = 750 pF; VCC = 3.0 V; HDMI5V = 5.3 V; Pulled up to HDMI5V using RPUHV; | 1250 | ns |