ZHCSLM6A december   2021  – june 2023 TDP0604

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  4-Level Inputs
      2. 8.3.2  I/O Voltage Level Selection
      3. 8.3.3  HPD_OUT
      4. 8.3.4  Lane Control
      5. 8.3.5  Swap
      6. 8.3.6  Linear and Limited Redriver
      7. 8.3.7  Main Link Inputs
      8. 8.3.8  Receiver Equalizer
      9. 8.3.9  CTLE Bypass
      10. 8.3.10 Input Signal Detect
      11. 8.3.11 Main Link Outputs
        1. 8.3.11.1 Transmitter Bias
        2. 8.3.11.2 Transmitter Impedance Control
        3. 8.3.11.3 TX Slew Rate Control
        4. 8.3.11.4 TX Pre-Emphasis and De-Emphasis Control
        5. 8.3.11.5 TX Swing Control
      12. 8.3.12 DDC Buffer
      13. 8.3.13 HDMI DDC Capacitance
      14. 8.3.14 DisplayPort
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Control
        1. 8.4.1.1 I2C Mode (MODE = "F")
        2. 8.4.1.2 Pin Strap Modes
          1. 8.4.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
      2. 8.4.2 DDC Snoop Feature
        1. 8.4.2.1 HDMI Type
      3. 8.4.3 Low Power Modes
    5. 8.5 Programming
      1. 8.5.1 Pseudocode Examples
        1. 8.5.1.1 HDMI 2.0 Source Example with DDC Snoop and DDC Buffer Enabled
      2. 8.5.2 TDP0604 I2C Address Options
      3. 8.5.3 I2C Target Behavior
    6. 8.6 Register Maps
      1. 8.6.1 TDP0604 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Source-Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pre-Channel (LAB)
        2. 9.2.2.2 Post-Channel (LCD)
        3. 9.2.2.3 Common Mode Choke
        4. 9.2.2.4 ESD Protection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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6.6 Timing Requirements

MIN NOM MAX UNIT
Local I2C (SCL/CFG0, SDA/CFG1). Refer to Figure 7-9.
fSCL I2C clock frequency 1 MHz
tBUF Bus free time between START and STOP conditions 0.5 µs
tHD_STA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs
tLOW Low period of the I2C clock 0.5 µs
tHIGH High period of the I2C clock 0.26 µs
tSU_STA Setup time for a repeated START condition 0.26 µs
tHD_DAT Data hold time 0 μs
tSU_DAT Data setup time 50 ns
tR Rise time of both SDA and SCL signals 120 ns
tF Fall time of both SDA and SCL signals 4 120 ns
tSU_STO Setup time for STOP condition 0.26 μs
DDC Snoop I2C Timings. Refer to Figure 7-9.
fSCL I2C DDC clock frequency 100 kHz
tBUF Bus free time between START and STOP conditions 4.7 µs
tHD_STA Hold time after repeated START condition. After this period, the first clock pulse is generated 4 µs
tLOW Low period of the I2C clock 4.7 µs
tHIGH High period of the I2C clock 4 µs
tSU_STA Setup time for a repeated START condition 4.7 µs
tHD_DAT Data hold time 0 μs
tSUDAT Data setup time 250 ns
tR Rise time of both SDA and SCL signals. Measured from 30% to 70%. 1000 ns
tF Fall time of both SDA and SCL signals  Measured from 70% to 30%. 300 ns
tSU_STO Setup time for STOP condition 4 μs
Cb_LV Capacitive load for each bus line on LV side 50 pF
Power-On. Refer to Figure 7-1.
tVCC_RAMP VCC supply ramp. Measured from 10% to 90%. 0.10 50 ms
tD_PG Internal POR de-assertion delay 5 ms
tVIO_SU VIO supply stable before reset(2) high. 100 µs
tCFG_SU Configuration pins(1) setup before reset(2) high. 0 µs
tCFG_HD Configuration pins(1) hold after reset(2)high. 500 µs
(1) Follow comprise the configuration pins:  MODE,  ADDR/EQ0, EQ1, TXSWG, TXSLEW, TXPRE, AC_EN, HPDOUT_SEL, DCGAIN
(2) Reset is the logical AND of internal POR and EN pin.