SLVSJB5A November 2025 – December 2025 MSPM0G5187
PRODMIX
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| fADCCLK | ADC clock frequency | 4 | 32 | MHz | |||
| tADC trigger | Software trigger minimum width | 3 | ADCCLK cycles | ||||
| tSample_step | Sampling time for step input | 12-bit mode, RS = 50Ω, Cpext = 10pF | 188 | ns | |||
| tSample_VREF | Sample time with VREF | ADC CHANNEL=28,12-bit mode, VDD as reference | 4 | µs | |||
| tSample_SupplyMon | Sample time with Supply Monitor (VDD/3) | ADC CHANNEL=31,12-bit mode,Internal reference(VRSEL=1h or 2h) | 5 | µs | |||
| tSample_USBMon | Sample time with VUSB Monitor (VUSB33/3) | ADC CHANNEL=30,12-bit mode,Internal reference(VRSEL=1h or 2h) | 5 | µs | |||