ZHCSDE8A February 2015 – October 2018 MSP430F67621A , MSP430F67641A
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK
External: UCLK Duty cycle = 50% ±10% |
fSYSTEM | MHz | |||
fSCL | SCL clock frequency | 2 V, 3 V | 0 | 400 | kHz | ||
tHD,STA | Hold time (repeated) START | fSCL = 100 kHz | 2 V, 3 V | 5.1 | µs | ||
fSCL > 100 kHz | 1.5 | ||||||
tSU,STA | Setup time for a repeated START | fSCL = 100 kHz | 2 V, 3 V | 5.1 | µs | ||
fSCL > 100 kHz | 1.4 | ||||||
tHD,DAT | Data hold time | 2 V, 3 V | 0.4 | µs | |||
tSU,DAT | Data setup time | fSCL = 100 kHz | 2 V, 3 V | 5.0 | µs | ||
fSCL > 100 kHz | 2 V, 3 V | 1.3 | |||||
tSU,STO | Setup time for STOP | fSCL = 100 kHz | 2 V, 3 V | 5.2 | µs | ||
fSCL > 100 kHz | 1.7 | ||||||
tSP | Pulse duration of spikes suppressed by input filter | UCGLITx = 0 | 2 V, 3 V | 75 | 220 | ns | |
UCGLITx = 1 | 35 | 120 | |||||
UCGLITx = 2 | 30 | 60 | |||||
UCGLITx = 3 | 20 | 35 | |||||
tTIMEOUT | Clock low time-out | UCCLTOx = 1 | 2 V, 3 V | 30 | ms | ||
UCCLTOx = 2 | 33 | ||||||
UCCLTOx = 3 | 37 |