SLVSHK4 December   2025 MCT8376Z-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings AUTO
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Slave Mode Timings
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  PWM Control Mode (1x PWM Mode)
        1. 7.3.2.1 Analog Hall Input Configuration
        2. 7.3.2.2 Digital Hall Input Configuration
        3. 7.3.2.3 Asynchronous Modulation
        4. 7.3.2.4 Synchronous Modulation
        5. 7.3.2.5 Motor Operation
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD and GVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Seven Level Input Pin
      10. 7.3.10 Current Sense Amplifier Output (SO)
      11. 7.3.11 Active Demagnetization
        1. 7.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 7.3.11.1.1 Automatic Synchronous Rectification in Commutation
          2. 7.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 7.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      12. 7.3.12 Cycle-by-Cycle Current Limit
        1. 7.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      13. 7.3.13 Hall Comparators (Analog Hall Inputs)
      14. 7.3.14 Advance Angle
      15. 7.3.15 FGOUT Signal
      16. 7.3.16 Protections
        1. 7.3.16.1 VM Supply Undervoltage Lockout (RESET)
        2. 7.3.16.2 AVDD Undervoltage Protection (AVDD_UV)
        3. 7.3.16.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.16.4 VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.16.5 Overvoltage Protections (OV)
        6. 7.3.16.6 Overcurrent Protection (OCP)
          1. 7.3.16.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.16.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.16.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.16.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.16.7 Motor Lock (MTR_LOCK)
          1. 7.3.16.7.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)
          2. 7.3.16.7.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b)
          3. 7.3.16.7.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)
          4. 7.3.16.7.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)
        8. 7.3.16.8 Thermal Warning (OTW)
        9. 7.3.16.9 Thermal Shutdown (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 7.4.2 DRVOFF Functionality
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI Format
  9. 8 Register Map
    1. 8.1 STATUS Registers
    2. 8.2 CONTROL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Hall Sensor Configuration and Connection
      1. 9.2.1 Typical Configuration
      2. 9.2.2 Open Drain Configuration
      3. 9.2.3 Series Configuration
      4. 9.2.4 Parallel Configuration
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
        1. 9.4.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

MCT8376Z-Q1 MCT8376Z-Q128-Pin VQFN With Exposed Thermal PadTop ViewFigure 5-1 MCT8376Z-Q128-Pin VQFN With Exposed Thermal PadTop View
Table 5-1 MCT8376Z-Q1 Pin Functions
PIN28-pin VQFN PackageTYPE(1)DESCRIPTION
NAMEMCT8376ZH-Q1MCT8376ZS-Q1
ADVANCE22-IAdvance angle level setting. This pin is a 7-level input pin set by an external resistor.
AGND88GNDDevice analog ground. Refer Section 9.4.1 for connections recommendation.
AVDD99PWR O3.3V internal regulator output. Connect an X5R or X7R, 1µF, 6.3V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 30mA externally.
GVDD1010PWR O5V internal regulator output. Connect an X5R or X7R, 1µF, 10V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 30mA externally.
BRAKE2525IHigh → Brake the motor when High by turning all low side MOSFETs ON Low → normal operation
CP11PWR OCharge pump output. Connect a X5R or X7R, 1µF, 16V ceramic capacitor between the CP and VM pins.
DIR23-IDirection pin for setting the direction of the motor rotation to clockwise or counterclockwise.
DRVOFF1111IWhen this pin is pulled high the six MOSFETs in the power stage are turned OFF making all outputs Hi-Z.
FG2727IMotor Speed indicator output. Open-drain output requires an external pull-up resistor to 1.8V to 5.0V. Motor Speed indicator can be set to different division factor of Hall signals.
GAIN_SLEW_tLOCK21-IMotor lock detection time setting, CSA Gain and Slew Rate setting
HNA1515IPhase A hall element negative input. Noise filter capacitors are desirable, connected between the positive and negative hall inputs.
HNB1717IPhase B hall element negative input. Noise filter capacitors are desirable, connected between the positive and negative hall inputs.
HNC1919IPhase C hall element negative input. Noise filter capacitors are desirable, connected between the positive and negative hall inputs.
HPA1414IPhase A hall element positive input. Noise filter capacitors are desirable, connected between the positive and negative hall inputs.
HPB1616IPhase B hall element positive input. Noise filter capacitors are desirable, connected between the positive and negative hall inputs.
HPC1818IPhase C hall element positive input. Noise filter capacitors are desirable, connected between the positive and negative hall inputs.
ILIMIT2828Sets the threshold for phase current used in cycle by cycle current limit.
MODE20-IPWM input mode and Hall configuration setting. This pin is a 7-level input pin set by an external resistor.
nFAULT1212OFault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 1.8V to 5.0V. If external supply is used to pull up nFAULT, verify that the external supply is pulled to >2.2V on power up.
nSCS-23ISerial chip select. A logic low on this pin enables serial interface communication.
nSLEEP1313IDriver nSLEEP. When this pin is logic low, the device goes into a low-power sleep mode. An 20 to 40µs low pulse can be used to reset fault conditions without entering sleep mode.
OUTA44PWR OHalf bridge output A
OUTB55PWR OHalf bridge output B
OUTC66PWR OHalf bridge output C
PGND3, 73, 7GNDDevice power ground. Refer Section 9.4.1 for connections recommendation.
PWM2626PWM input for motor control. Set the duty cycle and switching frequency of the phase voltage of the motor
SCLK-22ISerial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin (SPI devices).
SDI-21ISerial data input. Data is captured on the falling edge of the SCLK pin (SPI devices).
SDO-20OSerial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor (SPI devices).
SO2424OCurrent sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND).
VM22PWR IPower supply. Connect to motor supply voltage; bypass to PGND with a 0.1µF capacitor plus one bulk capacitor rated for VM. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
Thermal padGNDMust be connected to analog ground.
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect