ZHCSFO3D November   2016  – August 2021 LM5170-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息
Power MOSFETS

The power MOSFETs must be chosen with a VDS rating capable of withstanding the maximum HV-port voltage plus transient spikes (ringing). In this example, the maximum HV-rail voltage is 70 V. Selecting the 80 V rated MOSFETs will allow 10-V transient spikes.

When the voltage rating is determined, select the MOSFETs by making tradeoffs between the MOSFET Rds(ON) and total gate charge Qg to balance the conduction and switching losses. For high power applications, parallel MOSFETs to share total power and reduce the dissipation on any individual MOSFET, hence relieving the thermal stress. The conduction losses in each MOSFET is determined by Equation 53.

Equation 53. GUID-C51E81EE-4378-4DB3-9893-C4E2E49574FD-low.gif

where

  • N is the number of MOSFETs in parallel
  • 1.8 is the approximate temperature coefficient of the Rds(ON) at 125 °C
  • and the total RMS switch current IQ_RMS is approximately determined by Equation 54
Equation 54. GUID-E37C2344-0AE9-4695-BBCE-09E8A6703E68-low.gif

where

  • Dmax is the maximum duty cycle, either in the buck mode or boost mode.

The switching transient rise and fall times are approximately determined by:

Equation 55. GUID-10EA88DF-F456-4F15-86C3-CD2380401548-low.gif
Equation 56. GUID-EFDDB2FC-2DCD-4260-8701-549BA5283344-low.gif

And the switching losses of each of the paralleled MOSFETs are approximately determined by:

Equation 57. GUID-CA4A99F8-6C96-4B36-94BE-77AC1CFD2FAE-low.gif

where

  • Coss is the MOSFET’s output capacitance.

The power MOSFET usually requires a gate-to-source resistor of 10 kΩ to 100 kΩ to mitigate the effects of a failed gate drive. When using parallel MOSFETs, a good practice is to use 1- to 2-Ω gate resistor for each MOSFET, as shown in Figure 9-10.

GUID-DFD3E00E-E689-4AB1-8DA4-A1D127B62BDE-low.gifFigure 9-10 Paralleled MOSFET Configuration

If the dead time is not optimal, the body diode of the power synchronous rectifier MOSFET will cause losses in reverse recovery. Assuming the reverse recovery charge of the power MOSFET is Qrr, the reverse recovery losses are thus determined by Equation 58:

Equation 58. GUID-5B798976-875F-487C-BAD4-178C314B5AAC-low.gif

To reduce the reverse recovery losses, an optional Schottky diode can be placed in parallel with the power MOSFETs. The diode should have the same voltage rating as the MOSFET, and it must be placed directly across the MOSFETs drain and source. The peak repetitive forward current rating should be greater than Ipeak, and the continuous forward current rating should be greater than the following Equation 59:

Equation 59. GUID-FE4AC50E-1F9F-4B13-9DBA-05880AE35CCA-low.gif