Until SSSR capacitor reaches V_SSREn (1-V typical), the controller operates at SR synchronization (SYNC) mode where the SR pulses are synchronized to the respective primary FET pulses, as shown in Figure 7-10. This helps to reduce the conduction loss of the SRs. In addition, due to the fact that the SRs only conduct during power transfer phase, there is no risk of reverse current in SYNC mode. Since the pulse width of SRs gradually increases, the output voltage disturbance due to the difference in the voltage drop between the body diode and the on resistance of the SRs is prevented.

Once the SSSR capacitor crosses the V_SSREn, the LM5036 device begins the soft-start of the SRs freewheeling period (highlighted in gray in Figure 7-10) where the SRs may sink current from the output if they are engaged prematurely. The V_SSREn offset on the SSSR pin is intended to provide additional delay which ensures that the primary duty cycle ramps up to a point where the output voltage is in-regulation, thereby avoiding reverse current when the SRs are engaged. The SR soft-start follows a leading-edge modulation technique such that the leading-edge of the SR pulse is soft-started as opposed to the trailing-edge modulation of the primary FETs. As shown in Figure 7-10, SR1 and SR2 are turned on simultaneously with a narrow pulse-width during the freewheeling period. At the end of the freewheel period, that is, at the rising edge of the main CLK, the SR in phase with the next power transfer cycle remains on while the SR out of phase with it is turned off. The in-phase SR remains on throughout the power transfer cycle and at the end of it, both the primary FET and the in-phase SR are turned off simultaneously. At the end of the soft-start, the SR pulses will become complementary to the respective primary FETs, as shown in Figure 7-6.