Although the DLPC4420 controller requires an array of power supply voltages (1.1V, 1.8V, 3.3V), there are no restrictions regarding the relative order of power supply sequencing for both power-up and power-down scenarios. Similarly, there is no minimum time between powering-up or powering-down the different supplies feeding the DLP controller. However, note that it is not uncommon for there to be power sequencing requirements for the devices that share the supplies with the DLP controller.

• 1.1V core power is applied whenever any I/O power is applied to ensures the state of the associated I/O that are powered are controlled to a known state. Thus, it is recommended to apply core power first. Other supplies are applied only after the 1.1V core has ramped up.
• All DLPC4420 device power must be applied before POSENSE is asserted to ensure proper power-up initialization.

Typically the DLPC4420 controller power-up sequencing is handled by external hardware. An external power monitor will hold the controller in system reset during power-up (i.e. POSENSE = 0). During this time all DLP controller I/Os are tri-stated. The primary PLL (PLLM1) is released from reset upon the low to high transition of POSENSE but the controller keeps the rest of the device in reset for an additional 60 ms to allow the PLL to lock and stabilize its outputs. After this 60 ms delay the ARM-9 related internal resets are de-asserted causing the microprocessor to begin its boot-up routine.

Figure 9-1 System Power-Up Sequence