ZHCSO15A December   2021  – February 2023 DLPC4420

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements
    11. 6.11 DMD LVDS Interface Timing Requirements
    12. 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13 Programmable Output Clocks Switching Characteristics
    14. 6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
    15. 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Reset Operation
        1. 7.3.1.1 Power-Up Reset Operation
        2. 7.3.1.2 System Reset Operation
      2. 7.3.2 Spread Spectrum Clock Generator Support
      3. 7.3.3 GPIO Interface
      4. 7.3.4 Source Input Blanking
      5. 7.3.5 Video Graphics Processing Delay
      6. 7.3.6 Program Memory Flash/SRAM Interface
      7. 7.3.7 Calibration and Debug Support
      8. 7.3.8 Board Level Test Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC4420 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1V System Power
      3. 9.4.3 1.8V System Power
      4. 9.4.4 3.3V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC4420 Power
      2. 10.1.2 PCB Layout Guidelines for Auto-Lock Performance
      3. 10.1.3 DMD Interface Considerations
      4. 10.1.4 Layout Example
      5. 10.1.5 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Video Timing Parameter Definitions
      2. 11.2.2 Device Nomenclature
      3. 11.2.3 Device Markings
        1. 11.2.3.1 Device Marking
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage USB (9) 2.0 V
OSC (10) 2.0
3.3-V LVTTL (1,2,3,4) 2.0
3.3-V I2C (8) 2.4 VDD33VDD33+0.5
VIL Low-level input voltage USB (9) 0.8 V
OSC (10) 0.8
3.3-V LVTTL (1,2,3,4) 0.8
3.3-V I2C (8) –0.5 1.0
VDIS Differential Input Voltage USB(9) 200 mV
VICM Differential cross point voltage USB(9) 0.8 2.5 V
VHYS Hysteresis (VT+ –V T-) USB(9) 200 mV
3.3-V LVTTL (1,2,3,4) 400
3.3-V I2C (8) 300 550 600
VOH High-level output voltage USB (9) 2.8 V
1.8-V LVDS (7) 1.520
3.3-V LVTTL (1,2,3) IOH = Max Rated 2.7
VOL Low-level output voltage USB (9) 0.0 0.3 V
1.8-V LVDS (7) 0.880
3.3-V LVTTL (1,2,3) IOL = Max Rated 0.4
3.3-V I2C (8) IOL = 3-mA sink 0.4
VOD Output differential voltage 1.8-V LVDS (7) 0.065 0.440 V
IIH High-level input current USB(9) 200 µA
OSC (10) –10.0 10
3.3-V LVTTL (1-4) without internal pulldown VIH = VDD33 –10.0 10
3.3-V LVTTL (1-4) with internal pulldown VIH = VDD33 10.0 200.0
3.3-V I2C (8) VIH = VDD33 10.0
IIL Low-level input current USB(9) –10.0 10.0 µA
OSC (10) –10.0 10.0
3.3-V LVTTL (1–4) without internal pulldown VOH = VDD33 –10.0 10.0
3.3-V LVTTL (1-4) with internal pulldown VOH = VDD33 –10.0 –200
3.3-V I2C (8) VOH = VDD33 –10.0
IOH High-level output current USB(9) –19.1 mA
1.8-V LVDS (7) (VOD = 300 mV) VO = 1.4 V 6.5
3.3-V LVTTL (1) VO = 2.4 V –4.0
3.3-V LVTTL (2) VO = 2.4 V –8.0
3.3-V LVTTL (3) VO = 2.4 V –12.0
IOL Low-level output current USB (9) 19.1 mA
1.8-V LVDS (7) (VOD = 300 mV) VO = 1.0 V 6.5
3.3-V LVTTL (1) VO = 0.4 V 4.0
3.3-V LVTTL (2) VO = 0.4 V 8.0
3.3-V LVTTL (3) VO = 0.4 V 12.0
3.3-V I2C (8) 3.0
IOZ High-impedance leakage current USB (9) –10 pF
LVDS (7) –10
3.3-V LVTTL (1,2,3) –10
3.3-V I2C (8) –10
CI Input capacitance USB (9) 11.84 17.07 pF
3.3-V LVTTL (1) 3.75 5.52
3.3-V LVTTL (2) 3.75 5.52
3.3-V LVTTL (4) 3.75 5.52
3.3-V I2C (8) 5.26 6.54
ICC11 Supply voltage, 1.1-V core power Normal Mode 1474 mA
ICC18 Supply voltage, 1.8-V power (LVDS I/O and internal DRAM) Normal Mode 1005 mA
ICC33 Supply voltage, 3.3-V I/O power Normal Mode 33 mA
ICC11_PLLD Supply voltage, DMD PLL Digital Power ( 1.1 V) Normal Mode 4.4 6.2 mA
ICC11_PLLM1 Supply voltage, Master-LS Clock Generator PLL Digital power ( 1.1 V) Normal Mode 4.4 6.2 mA
ICC11_PLLM2 Supply voltage, Master-HS Clock Generator PLL Digital power ( 1.1 V) Normal Mode 4.4 6.2 mA
ICC18_PLLD Supply voltage, DMD PLL Analog Power (1.8 V) Normal Mode 8.0 10.2 mA
ICC18_PLLM1 Supply voltage, Master-LS Clock Generator PLL Analog power (1.8 V) Normal Mode 8.0 10.2 mA
ICC18_PLLM2 Supply voltage, Master-HS Clock Generator PLL Analog power (1.8 V) Normal Mode 8.0 10.2 mA
ICC11_PLLS Supply voltage, Video-2X PLL Analog Power ( 1.1 V) Normal Mode 2.9 mA
Total Power Normal Mode 3.73 W
ICC11 Supply voltage, 1.1 V core power Low Power Mode 21 mA
ICC18 Supply voltage, 1.8-V power (LVDS I/O and internal DRAM) Low Power Mode 0 mA
ICC33 Supply voltage, 3.3-V I/O power Low Power Mode 18 mA
ICC11_PLLD Supply voltage, DMD PLL Digital Power ( 1.1 V) Low Power Mode 2.03 mA
ICC11_PLLM1 Supply voltage, Master-LS Clock Generator PLL Digital power ( 1.1 V) Low Power Mode 2.03 mA
ICC11_PLLM2 Supply voltage, Master-HS Clock Generator PLL Digital power ( 1.1 V) Low Power Mode 2.03 mA
ICC18_PLLD Supply voltage, DMD PLL Analog Power (1.8 V) Low Power Mode 5.42 mA
ICC18_PLLM1 Supply voltage, Master-LS Clock Generator PLL Analog power (1.8 V) Low Power Mode 5.42 mA
ICC18_PLLM2 Supply voltage, Master-HS Clock Generator PLL Analog power (1.8 V) Low Power Mode 5.42 mA
ICC11_PLLS Supply voltage, Video-2X PLL Analog Power ( 1.1 V) Low Power Mode .03 mA
Total Power Low Power Mode 106 mW